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Searched refs:isBeforeLegalize (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1604 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1620 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1780 if (!DCI.isBeforeLegalize() || in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp600 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
616 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
2725 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts()
3946 !DCI.isBeforeLegalize()); in foldSetCCWithBinOp()
4217 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
4304 if (DCI.isBeforeLegalize() && in SimplifySetCC()
4756 getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC()
4782 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC()
6147 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareUREMEqFold()
6396 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareSREMEqFold()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2855 if (!DCI.isBeforeLegalize()) in performLoadCombine()
2908 if (!DCI.isBeforeLegalize()) in performStoreCombine()
4121 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
H A DSIISelLowering.cpp9573 if (DCI.isBeforeLegalize()) in performAndCombine()
10658 if (Vec.hasOneUse() && DCI.isBeforeLegalize()) { in performExtractVectorEltCombine()
10711 if (!DCI.isBeforeLegalize()) in performExtractVectorEltCombine()
11539 if (!DCI.isBeforeLegalize()) { in PerformDAGCombine()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3820 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } in isBeforeLegalize() function
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp15047 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performFirstTrueTestVectorCombine()
15077 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performLastTrueTestVectorCombine()
16243 if (DCI.isBeforeLegalize()) in tryConvertSVEWideCompare()
17535 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in performTBISimplification()
17761 if (!DCI.isBeforeLegalize()) in performMaskedGatherScatterCombine()
17797 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in performNEONPostLDSTCombine()
18400 if (DCI.isBeforeLegalize() && VT.isScalarInteger() && in performSETCCCombine()
18781 assert(DCI.isBeforeLegalize() || in performSelectCombine()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12488 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineBUILD_VECTORToVPADDL()
13308 if (DCI.isBeforeLegalize()) return SDValue(); in PerformADDECombine()
13687 if (DCI.isBeforeLegalize()) in PerformSHLSimplify()
13992 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMULCombine()
14070 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in CombineANDShift()
16039 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformVLDCombine()
16047 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMVEVLDCombine()
17418 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformShiftCombine()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp42635 if (DCI.isBeforeLegalize()) { in combineBitcast()
44434 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in combineVSelectToBLENDV()
44983 if (DCI.isBeforeLegalize() && !Subtarget.hasAVX512() && in combineSelect()
45885 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov()
46372 if (DCI.isBeforeLegalize() && VT.isVector()) in combineMul()
46384 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in combineMul()
49009 RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) { in combineLoad()
49527 if (DCI.isBeforeLegalize() || TLI.isTypeLegal(St->getMemoryVT())) in combineStore()
52139 isNullConstant(RHS) && !DCI.isBeforeLegalize()) { in combineSetCC()
52386 if (DCI.isBeforeLegalize()) { in combineGatherScatter()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14389 if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) { in DAGCombineBuildVector()
15212 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
15643 if (!DCI.isBeforeLegalize() || !Is64BitBswapOn64BitTgt || in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp9126 if (!DCI.isBeforeLegalize()) in PerformDAGCombine()