Home
last modified time | relevance | path

Searched refs:insertPass (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetMachine.cpp1278 insertPass(&PHIEliminationID, &SILowerControlFlowID); in addFastRegAlloc()
1280 insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID); in addFastRegAlloc()
1281 insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID); in addFastRegAlloc()
1289 insertPass(&MachineSchedulerID, &SIWholeQuadModeID); in addOptimizedRegAlloc()
1290 insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID); in addOptimizedRegAlloc()
1293 insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID); in addOptimizedRegAlloc()
1296 insertPass(&RenameIndependentSubregsID, &GCNPreRAOptimizationsID); in addOptimizedRegAlloc()
1301 insertPass(&MachineSchedulerID, &SIFormMemoryClausesID); in addOptimizedRegAlloc()
1308 insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID); in addOptimizedRegAlloc()
1312 insertPass(&PHIEliminationID, &SILowerControlFlowID); in addOptimizedRegAlloc()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetPassConfig.h190 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
H A DCodeGenPassBuilder.h214 template <typename PassT> void insertPass(AnalysisKey *ID, PassT Pass) { in insertPass() function
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonTargetMachine.cpp413 insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID); in addPreRegAlloc()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp527 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID, in addPreRegAlloc()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetPassConfig.cpp649 void TargetPassConfig::insertPass(AnalysisID TargetPassID, in insertPass() function in TargetPassConfig