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Searched refs:hasSuperClassEq (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
271 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
514 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
515 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
531 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
537 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
H A DThumb1InstrInfo.cpp112 (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
116 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp1666 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
1667 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
1669 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1703 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1704 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1705 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1707 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
1708 bool Is256Bit = OpRC->hasSuperClassEq(&X86::VR256XRegClass); in hardenLoadAddr()
1736 assert(OpRC->hasSuperClassEq(&X86::GR64RegClass) && in hardenLoadAddr()
1892 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]); in canHardenRegister()
H A DX86RegisterInfo.cpp224 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()
225 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit) in shouldRewriteCopySrc()
H A DX86ISelLowering.cpp55900 return RC.hasSuperClassEq(&X86::GR8RegClass) || in isGRClass()
55901 RC.hasSuperClassEq(&X86::GR16RegClass) || in isGRClass()
55902 RC.hasSuperClassEq(&X86::GR32RegClass) || in isGRClass()
55903 RC.hasSuperClassEq(&X86::GR64RegClass) || in isGRClass()
55915 RC.hasSuperClassEq(&X86::VR512RegClass); in isFRClass()
55921 return RC.hasSuperClassEq(&X86::VK1RegClass) || in isVKClass()
55922 RC.hasSuperClassEq(&X86::VK2RegClass) || in isVKClass()
55923 RC.hasSuperClassEq(&X86::VK4RegClass) || in isVKClass()
55924 RC.hasSuperClassEq(&X86::VK8RegClass) || in isVKClass()
55925 RC.hasSuperClassEq(&X86::VK16RegClass) || in isVKClass()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp472 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()
492 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()
626 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitStore()
1284 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in SelectBinaryIntOp()
2125 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCMaterialize32BitInt()
H A DPPCInstrInfo.cpp183 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
184 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
5104 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp389 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h139 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() function
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineCombiner.cpp188 return SrcRC->hasSuperClassEq(DstRC) || SrcRC->hasSubClassEq(DstRC); in isTransientMI()
H A DMachineVerifier.cpp2155 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp3038 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
3040 return RC.hasSuperClassEq(getAGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
3042 return RC.hasSuperClassEq( in isProperlyAlignedRC()
H A DSIInstrInfo.cpp1091 if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) { in materializeImmediate()
4962 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()
8203 if (RC->hasSuperClassEq(&AMDGPU::SReg_32RegClass)) { in foldMemoryOperandImpl()
8206 } else if (RC->hasSuperClassEq(&AMDGPU::SReg_64RegClass)) { in foldMemoryOperandImpl()
H A DAMDGPUInstructionSelector.cpp88 RC->hasSuperClassEq(TRI.getBoolRC()); in isVCC()