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Searched refs:has16BitInsts (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp328 return (ElemWidth == 16 && ST->has16BitInsts()) ? 2 in getMaximumVF()
538 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
553 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
564 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
580 if (ST->has16BitInsts() && SLT == MVT::f16 && !HasFP64FP16Denormals) in getArithmeticInstrCost()
599 if (ST->has16BitInsts() && SLT == MVT::f16) in getArithmeticInstrCost()
623 (SLT == MVT::f16 && ST->has16BitInsts())) { in getArithmeticInstrCost()
628 if (SLT == MVT::f16 && ST->has16BitInsts()) { in getArithmeticInstrCost()
703 if ((ST->has16BitInsts() && SLT == MVT::f16) || in getIntrinsicInstrCost()
799 if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) in getVectorInstrCost()
H A DAMDGPUSubtarget.h146 bool has16BitInsts() const { in has16BitInsts() function
H A DAMDGPUCodeGenPrepare.cpp515 if (Size <= 16 && ST->has16BitInsts()) in replaceMulWithMul24()
770 if (Ty->isHalfTy() && !ST->has16BitInsts()) in visitFDiv()
1236 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBinaryOperator()
1366 if (ST->has16BitInsts() && needsPromotionToI32(I.getOperand(0)->getType()) && in visitICmpInst()
1376 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitSelectInst()
1395 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBitreverseIntrinsicInst()
H A DAMDGPULegalizerInfo.cpp713 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
763 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
799 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
829 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
860 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()
871 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()
891 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
935 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
953 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()
961 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()
[all …]
H A DAMDGPUISelLowering.cpp623 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts())); in isFPImmLegal()
758 (Subtarget->has16BitInsts() && VT == MVT::f16); in isFAbsFree()
801 if (DestSize== 16 && Subtarget->has16BitInsts()) in isTruncateFree()
811 if (SrcSize == 16 && Subtarget->has16BitInsts()) in isZExtFree()
2455 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()
2494 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerSINT_TO_FP()
3307 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()
3467 if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() && in getFFBX_U32()
3914 assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal"); in performFAbsCombine()
H A DSIISelLowering.cpp130 if (Subtarget->has16BitInsts()) { in SITargetLowering()
392 if (Subtarget->has16BitInsts()) { in SITargetLowering()
455 if (Subtarget->has16BitInsts()) { in SITargetLowering()
681 if (Subtarget->has16BitInsts()) { in SITargetLowering()
825 if (Subtarget->has16BitInsts()) in getRegisterTypeForCallingConv()
853 if (Size == 16 && Subtarget->has16BitInsts()) in getNumRegistersForCallingConv()
878 if (Size == 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()
892 if (Size < 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()
1609 if (Subtarget->has16BitInsts() && VT == MVT::i16) { in isTypeDesirableForOp()
9908 if (!Subtarget->has16BitInsts() || in performZeroExtendCombine()
[all …]
H A DAMDGPU.td1589 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
H A DSIInstrInfo.cpp3597 return ST.has16BitInsts() && in isInlineConstant()
3669 return ST.has16BitInsts() && in isInlineConstant()