Lines Matching refs:has16BitInsts

130   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
392   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
455   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
681   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
825       if (Subtarget->has16BitInsts())  in getRegisterTypeForCallingConv()
831       return Subtarget->has16BitInsts() ? MVT::i16 : MVT::i32;  in getRegisterTypeForCallingConv()
853     if (Size == 16 && Subtarget->has16BitInsts())  in getNumRegistersForCallingConv()
878     if (Size == 16 && Subtarget->has16BitInsts()) {  in getVectorTypeBreakdownForCallingConv()
892     if (Size < 16 && Subtarget->has16BitInsts()) {  in getVectorTypeBreakdownForCallingConv()
1609   if (Subtarget->has16BitInsts() && VT == MVT::i16) {  in isTypeDesirableForOp()
4470   return (Ty.getScalarSizeInBits() <= 16 && Subtarget->has16BitInsts())  in getPreferredShiftAmountTy()
4512     return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF);  in isFMAFasterThanFMulAndFAdd()
9908   if (!Subtarget->has16BitInsts() ||  in performZeroExtendCombine()
10506        (VT == MVT::f16 && Subtarget->has16BitInsts()) ||  in performMinMaxCombine()
11330   if (VT != MVT::f32 && VT != MVT::f64 && (Subtarget->has16BitInsts() &&  in performSetCCCombine()
12257   if (Size == 16 && !Subtarget->has16BitInsts())  in getAsmOperandConstVal()