| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypes.h | 274 return DAG.getZeroExtendInReg(Op, dl, OldVT); in ZExtPromotedInteger()
288 return DAG.getZeroExtendInReg(Op, DL, OldVT); in SExtOrZExtPromotedInteger()
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| H A D | LegalizeDAG.cpp | 554 Value = DAG.getZeroExtendInReg(Value, dl, StVT); in LegalizeStoreOps()
935 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); in LegalizeLoadOps()
2822 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
2826 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType); in ExpandNode()
2827 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
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| H A D | LegalizeIntegerTypes.cpp | 756 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); in PromoteIntRes_INT_EXTEND()
1320 Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT); in PromoteIntRes_FunnelShift()
1431 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); in PromoteIntRes_UADDSUBO()
2148 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); in PromoteIntOp_ZERO_EXTEND()
4589 Hi = DAG.getZeroExtendInReg(Hi, dl, in ExpandIntRes_ZERO_EXTEND()
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| H A D | DAGCombiner.cpp | 1338 return DAG.getZeroExtendInReg(NewOp, DL, OldVT); in ZExtPromoteOperand()
12278 Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT); in visitZERO_EXTEND()
12290 SDValue And = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT); in visitZERO_EXTEND()
12422 return DAG.getZeroExtendInReg(VSetCC, DL, N0.getValueType()); in visitZERO_EXTEND()
12432 return DAG.getZeroExtendInReg(DAG.getAnyExtOrTrunc(VsetCC, DL, VT), DL, in visitZERO_EXTEND()
13043 return DAG.getZeroExtendInReg(N0, SDLoc(N), ExtVT); in visitSIGN_EXTEND_INREG()
24191 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), VT); in SimplifySelectCC()
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| H A D | SelectionDAG.cpp | 1388 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg() function in SelectionDAG
1415 return getZeroExtendInReg(Op, DL, VT); in getPtrExtendInReg()
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| H A D | TargetLowering.cpp | 2201 return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT)); in SimplifyDemandedBits()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 981 Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8); in LowerShifts()
991 : DAG.getZeroExtendInReg(Victim, dl, MVT::i8); in LowerShifts()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1054 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1287 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT); in lowerPrivateExtLoad()
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| H A D | AMDGPUISelLowering.cpp | 4089 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
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| H A D | SIISelLowering.cpp | 8586 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2482 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8); in buildVector32()
2638 ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy)); in extractVector()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 888 SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 25674 StoredVal = DAG.getZeroExtendInReg( in LowerStore()
47454 return DAG.getZeroExtendInReg(Op, DL, NarrowVT); in PromoteMaskArithmetic()
49375 Val = DAG.getZeroExtendInReg(Val, dl, MVT::i1); in combineStore()
51662 Res = DAG.getZeroExtendInReg(Res, dl, N0.getValueType()); in combineExtSetcc()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 18492 : DAG.getZeroExtendInReg(VVT, DL, ExtVT); in PerformMVEExtCombine()
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