| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblySelectionDAGInfo.cpp | 33 DAG.getZExtOrTrunc(Size, DL, LenMVT)}); in EmitTargetCodeForMemcpy() 58 DAG.getZExtOrTrunc(Size, DL, LenMVT)); in EmitTargetCodeForMemset()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 55 DAG.getZExtOrTrunc(Size, DL, MVT::i64), in emitMemMemReg() 194 Length = DAG.getZExtOrTrunc(Length, DL, PtrVT); in EmitTargetCodeForMemchr() 195 Char = DAG.getZExtOrTrunc(Char, DL, MVT::i32); in EmitTargetCodeForMemchr() 266 MaxLength = DAG.getZExtOrTrunc(MaxLength, DL, PtrVT); in EmitTargetCodeForStrnlen()
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| H A D | SystemZISelLowering.cpp | 5863 Success = DAG.getZExtOrTrunc(Success, DL, N->getValueType(1)); in LowerOperationWrapper() 6489 Word = DAG.getZExtOrTrunc(LHS->getOperand(0), SDLoc(SN), WordVT); in combineSTORE()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.cpp | 180 DAG.getZExtOrTrunc(Size, dl, MVT::i32)); in EmitTargetCodeForMemcpy() 314 DAG.getZExtOrTrunc(Size, dl, MVT::i32)); in EmitTargetCodeForMemset()
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| H A D | ARMISelLowering.cpp | 6625 ShAmt = DAG.getZExtOrTrunc(ShAmt, dl, MVT::i32); in Expand64BitShift() 13282 DCI.DAG.getZExtOrTrunc(Op1S, DL, MVT::i32)); in PerformVSetCCToVCTPCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2610 UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32); in LowerFP_TO_FP16() 2611 U = DAG.getZExtOrTrunc(U, DL, MVT::i32); in LowerFP_TO_FP16() 2682 return DAG.getZExtOrTrunc(V, DL, Op.getValueType()); in LowerFP_TO_FP16() 3077 return DAG.getZExtOrTrunc(Shl, SL, VT); in performShlCombine() 3329 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulCombine() 3330 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32); in performMulCombine() 3370 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulLoHiCombine() 3371 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32); in performMulLoHiCombine() 3447 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulhuCombine() 3448 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32); in performMulhuCombine() [all …]
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| H A D | SIISelLowering.cpp | 1706 Val = DAG.getZExtOrTrunc(Val, SL, VT); in convertArgType() 4901 return DAG.getZExtOrTrunc(SetCC, DL, VT); in lowerICMPIntrinsic() 4931 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic() 4967 AMDGPUISD::SETCC, SL, VT, DAG.getZExtOrTrunc(Src, SL, MVT::i32), in lowerBALLOTIntrinsic() 11382 SDValue Shifted = DAG.getZExtOrTrunc(Shift.getOperand(0), in performCvtF32UByteNCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2370 SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32); in LowerBITCAST() 2441 E0 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[0]), dl, MVT::i32); in buildVector32() 2442 E1 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[1]), dl, MVT::i32); in buildVector32() 2471 SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32); in buildVector32() 2481 Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32); in buildVector32() 2534 SDValue Ext = DAG.getZExtOrTrunc(S, dl, MVT::i32); in buildVector64() 2648 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32); in extractVector() 2656 ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy)); in extractVector() 2718 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32); in insertVector()
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| H A D | HexagonISelLoweringHVX.cpp | 945 SDValue Ext = !V.isUndef() ? DAG.getZExtOrTrunc(V, dl, MVT::i8) in buildHvxVectorPred() 965 SDValue Ext = (B < 8) ? DAG.getZExtOrTrunc(F, dl, MVT::i8) in buildHvxVectorPred() 1837 return DAG.getZExtOrTrunc(W0, dl, ResTy); in LowerHvxBitcast()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1023 LHS = DAG.getZExtOrTrunc(LHS, dl, WideVT); in earlyExpandDIVFIX() 1024 RHS = DAG.getZExtOrTrunc(RHS, dl, WideVT); in earlyExpandDIVFIX() 1039 return DAG.getZExtOrTrunc(Res, dl, VT); in earlyExpandDIVFIX() 1921 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N), in PromoteIntOp_INSERT_VECTOR_ELT() 2978 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT); in ExpandIntRes_ADDSUB() 2995 SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT); in ExpandIntRes_ADDSUB() 3017 Borrow = DAG.getZExtOrTrunc(Cmp, dl, NVT); in ExpandIntRes_ADDSUB() 4196 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift() 4243 SDValue ShAmt = DAG.getZExtOrTrunc(N->getOperand(1), dl, ShAmtTy); in ExpandIntRes_Shift() 5505 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, in PromoteIntOp_EXTRACT_VECTOR_ELT()
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| H A D | DAGCombiner.cpp | 4008 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT); in visitMUL() 4400 C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy); in visitSDIVLike() 4756 SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT); in visitMULHU() 6052 SDValue X = DAG.getZExtOrTrunc(Src, DL, VT); in combineShiftAnd1ToBitTest() 6059 return DAG.getZExtOrTrunc(Setcc, DL, VT); in combineShiftAnd1ToBitTest() 9942 Res = DAG.getZExtOrTrunc(Res, DL, HalfVT); in visitBSWAP() 9944 return DAG.getZExtOrTrunc(Res, DL, VT); in visitBSWAP() 10244 return DAG.getZExtOrTrunc(NotCond, DL, VT); in foldSelectOfConstants() 10827 SDValue ZextCond = DAG.getZExtOrTrunc(Cond, DL, VT); in foldVSelectOfConstants() 12252 return DAG.getZExtOrTrunc(Op, SDLoc(N), VT); in visitZERO_EXTEND() [all …]
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| H A D | SelectionDAGBuilder.cpp | 2793 Sub = DAG.getZExtOrTrunc(Sub, dl, VT); in visitBitTestHeader() 3048 Ops[0] = DAG.getZExtOrTrunc( in visitLandingPad() 3056 Ops[1] = DAG.getZExtOrTrunc( in visitLandingPad() 3163 Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy); in visitShift() 3483 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT); in visitPtrToInt() 3494 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), PtrMemVT); in visitIntToPtr() 4153 L = DAG.getZExtOrTrunc(L, dl, ValueVTs[i]); in visitLoad() 5446 LHS = DAG.getZExtOrTrunc(LHS, DL, PromVT); in expandDivFix() 5447 RHS = DAG.getZExtOrTrunc(RHS, DL, PromVT); in expandDivFix() 5459 return DAG.getZExtOrTrunc(Res, DL, VT); in expandDivFix() [all …]
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| H A D | TargetLowering.cpp | 7363 DAG.getZExtOrTrunc(ExponentLoBit, dl, IntShVT)); in expandFP_TO_SINT() 7368 DAG.getZExtOrTrunc(SignLowBit, dl, IntShVT)); in expandFP_TO_SINT() 7375 R = DAG.getZExtOrTrunc(R, dl, DstVT); in expandFP_TO_SINT() 7380 DAG.getZExtOrTrunc( in expandFP_TO_SINT() 7384 DAG.getZExtOrTrunc( in expandFP_TO_SINT() 8666 Increment = DAG.getZExtOrTrunc(Increment, DL, AddrVT); in IncrementMemoryAddress() 8730 Index = DAG.getZExtOrTrunc(Index, dl, VecPtr.getValueType()); in getVectorSubVecPointer()
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| H A D | SelectionDAG.cpp | 1373 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getZExtOrTrunc() function in SelectionDAG 1409 return getZExtOrTrunc(Op, DL, VT); in getPtrExtOrTrunc() 2203 return getZExtOrTrunc(Op, SDLoc(Op), ShTy); in getShiftAmountOperand() 4928 ? DAG.getZExtOrTrunc(Op, DL, SVT) in foldCONCAT_VECTORS()
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| H A D | LegalizeDAG.cpp | 3473 DAG.getNode(ISD::AND, dl, VT, DAG.getZExtOrTrunc(Carry, dl, VT), One); in ExpandNode() 3485 DAG.getZExtOrTrunc(Carry, dl, SetCCType)); in ExpandNode()
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| H A D | LegalizeVectorTypes.cpp | 3082 return DAG.getZExtOrTrunc(Load, dl, N->getValueType(0)); in SplitVecOp_EXTRACT_VECTOR_ELT()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23329 Res = DAG.getZExtOrTrunc(Res, dl, VT); in LowerFGETSIGN() 30150 Amt = DAG.getZExtOrTrunc(Amt, dl, ExVT); in LowerShift() 30161 return DAG.getZExtOrTrunc(R, dl, VT); in LowerShift() 30537 return DAG.getZExtOrTrunc(Res, DL, VT); in LowerFunnelShift() 31253 return DAG.getZExtOrTrunc(V, DL, DstVT); in LowerBITCAST() 42283 return DAG.getZExtOrTrunc(V, DL, VT); in combineBitcastvxi1() 42395 V = DAG.getZExtOrTrunc(V, DL, IntVT); in combineBitcastvxi1() 42965 LHS = DAG.getZExtOrTrunc(LHS, DL, Vi8VT); in createVPDPBUSD() 43472 Scl = DAG.getZExtOrTrunc(Scl, dl, VT); in combineExtractWithShuffle() 43587 return DAG.getZExtOrTrunc(V, dl, VT); in combineExtractWithShuffle() [all …]
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| H A D | X86ISelDAGToDAG.cpp | 4015 Add0 = CurDAG->getZExtOrTrunc(Add0, DL, SubVT); in tryShiftAmountMod() 4936 SDValue ZextTarget = CurDAG->getZExtOrTrunc(Target, dl, MVT::i64); in Select()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 6203 Val = DAG.getZExtOrTrunc(Val, DL, VA.getValVT()); in LowerCallResult() 6671 Arg = DAG.getZExtOrTrunc(Arg, DL, VA.getLocVT()); in LowerCall() 7018 Arg = DAG.getZExtOrTrunc(Arg, DL, VA.getLocVT()); in LowerReturn() 7022 Arg = DAG.getZExtOrTrunc(Arg, DL, VA.getLocVT()); in LowerReturn() 8505 Stack = DAG.getZExtOrTrunc(Stack, DL, PtrMemVT); in LowerAAPCS_VASTART() 8521 GRTop = DAG.getZExtOrTrunc(GRTop, DL, PtrMemVT); in LowerAAPCS_VASTART() 8539 VRTop = DAG.getZExtOrTrunc(VRTop, DL, PtrMemVT); in LowerAAPCS_VASTART() 8612 VAList = DAG.getZExtOrTrunc(VAList, DL, PtrVT); in LowerVAARG() 8643 VANext = DAG.getZExtOrTrunc(VANext, DL, PtrMemVT); in LowerVAARG() 16337 return DAG.getZExtOrTrunc(Res, DL, VT); in getPTest() [all …]
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 884 SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7474 VA.getLocReg(), DAG.getZExtOrTrunc(ArgAsInt, dl, LocVT))); in LowerCall_AIX() 7484 GPR1.getLocReg(), DAG.getZExtOrTrunc(MSWAsI64, dl, MVT::i32))); in LowerCall_AIX() 7494 GPR2.getLocReg(), DAG.getZExtOrTrunc(ArgAsInt, dl, MVT::i32))); in LowerCall_AIX() 13855 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0))); in DAGCombineExtBoolTrunc() 13918 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0)); in DAGCombineExtBoolTrunc()
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