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Searched refs:getSubRegIndexLaneMask (Results 1 – 25 of 29) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp251 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
312 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
319 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
323 DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
447 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
455 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
H A DLiveIntervalCalc.cpp61 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
161 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
H A DTargetRegisterInfo.cpp535 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx); in getCoveringSubRegIndexes()
562 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx); in getCoveringSubRegIndexes()
567 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx); in getCoveringSubRegIndexes()
589 LanesLeft &= ~getSubRegIndexLaneMask(BestIdx); in getCoveringSubRegIndexes()
H A DLiveRangeEdit.cpp139 LaneBitmask LM = TRI->getSubRegIndexLaneMask(MO.getSubReg()); in allUsesAvailableAt()
267 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in useIsKill()
396 Alloc, TRI->getSubRegIndexLaneMask(DestSubReg)); in eliminateDeadDef()
H A DRenameIndependentSubregs.cpp183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
H A DRegisterCoalescer.cpp1492 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(NewIdx); in reMaterializeTrivialDef()
1628 LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx); in eliminateUndefCopy()
1667 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx); in eliminateUndefCopy()
1686 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg()); in eliminateUndefCopy()
1721 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
1804 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
1878 LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in setUndefOnPrunedSubRegUses()
2569 L |= TRI->getSubRegIndexLaneMask( in computeWriteLanes()
2867 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes).none()) in analyzeValue()
2876 LaneBitmask OtherMask = TRI->getSubRegIndexLaneMask(Other.SubIdx); in analyzeValue()
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H A DLiveIntervals.cpp572 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
790 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in addKillFlags()
1032 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1049 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1465 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none()) in findLastUseBefore()
1600 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in repairOldRegInRange()
H A DLivePhysRegs.cpp167 if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any()) in addBlockLiveIns()
H A DRDFRegisters.cpp187 LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex()); in aliasRM()
H A DLiveInterval.cpp895 LaneBitmask OrigMask = TRI.getSubRegIndexLaneMask(MOI->getSubReg()); in stripValuesNotDefiningMask()
975 LaneBitmask DefMask = TRI.getSubRegIndexLaneMask(SubReg); in computeSubRangeUndefs()
H A DVirtRegMap.cpp398 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
H A DPeepholeOptimizer.cpp1983 !(TRI->getSubRegIndexLaneMask(DefSubReg) & in getNextSourceFromInsertSubreg()
1984 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none()) in getNextSourceFromInsertSubreg()
H A DRegisterPressure.cpp557 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1236 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
H A DMachineVerifier.cpp2350 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
2442 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
2932 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none()) in verifyLiveRangeValue()
3068 LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) in verifyLiveRangeSegment()
H A DTwoAddressInstructionPass.cpp1579 RemainingUses |= TRI->getSubRegIndexLaneMask(MO.getSubReg()); in processTiedPairs()
1814 TRI->getSubRegIndexLaneMask(mi->getOperand(0).getSubReg()); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp178 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg()); in canBundle()
228 ? TRI->getSubRegIndexLaneMask(MO.getSubReg()) in collectRegUses()
H A DGCNRegPressure.cpp196 MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg()); in getDefRegMask()
205 return MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(SubReg); in getUsedRegMask()
H A DSIRegisterInfo.h380 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg)); in getNumChannelsFromSubReg()
H A DSIRegisterInfo.cpp323 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 && in SIRegisterInfo()
324 getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) && in SIRegisterInfo()
325 (getSubRegIndexLaneMask(AMDGPU::lo16) | in SIRegisterInfo()
326 getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() == in SIRegisterInfo()
327 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() && in SIRegisterInfo()
2974 LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg) in findReachingDef()
H A DSIShrinkInstructions.cpp521 LaneBitmask Overlap = TRI->getSubRegIndexLaneMask(SubReg) & in instAccessReg()
522 TRI->getSubRegIndexLaneMask(MO.getSubReg()); in instAccessReg()
H A DSIOptimizeExecMaskingPreRA.cpp247 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(CC->getSubReg()); in optimizeVcndVcmpPair()
H A DSIWholeQuadMode.cpp328 SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in markDefs()
390 : TRI->getSubRegIndexLaneMask(Op.getSubReg()); in markDefs()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DRDFCopy.cpp127 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex())) in run()
H A DHexagonBlockRanges.cpp246 if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any()) in getLiveIns()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h378 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() function

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