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Searched refs:getSchedulingPreference (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp262 TLI->getSchedulingPreference() == Sched::Source) in createDefaultScheduler()
264 if (TLI->getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
266 if (TLI->getSchedulingPreference() == Sched::Hybrid) in createDefaultScheduler()
268 if (TLI->getSchedulingPreference() == Sched::VLIW) in createDefaultScheduler()
270 if (TLI->getSchedulingPreference() == Sched::Fast) in createDefaultScheduler()
272 if (TLI->getSchedulingPreference() == Sched::Linearize) in createDefaultScheduler()
274 assert(TLI->getSchedulingPreference() == Sched::ILP && in createDefaultScheduler()
H A DScheduleDAGSDNodes.cpp85 SU->SchedulingPref = TLI.getSchedulingPreference(N); in newSUnit()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h591 Sched::Preference getSchedulingPreference(SDNode *N) const override;
H A DARMISelLowering.cpp1939 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { in getSchedulingPreference() function in ARMTargetLowering
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h873 Sched::Preference getSchedulingPreference(SDNode *N) const override;
H A DPPCISelLowering.cpp16827 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { in getSchedulingPreference() function in PPCTargetLowering
16829 return TargetLowering::getSchedulingPreference(N); in getSchedulingPreference()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h881 Sched::Preference getSchedulingPreference() const { in getSchedulingPreference() function
888 virtual Sched::Preference getSchedulingPreference(SDNode *) const { in getSchedulingPreference() function