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Searched refs:getRegClass (Results 1 – 25 of 214) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp67 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough()
149 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
H A DWebAssemblyExplicitLocals.cpp274 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
307 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
379 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
415 typeForRegClass(MRI.getRegClass(Reg))); in runOnMachineFunction()
H A DWebAssemblyMemIntrinsicResults.cpp170 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg)) in optimizeCall()
H A DWebAssemblyRegColoring.cpp140 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
145 if (MRI->getRegClass(SortedIntervals[C]->reg()) != RC) in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterBank.cpp35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
H A DRegAllocBase.cpp106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); in allocatePhysRegs()
184 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); in enqueue()
H A DPeepholeOptimizer.cpp477 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
488 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
574 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
603 RC = MRI->getRegClass(UseMI->getOperand(0).getReg()); in INITIALIZE_PASS_DEPENDENCY()
689 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource()
751 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); in findNextSource()
781 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
1252 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1440 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg)) in foldRedundantCopy()
1975 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) || in getNextSourceFromInsertSubreg()
H A DDetectDeadLanes.cpp152 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy()
248 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
367 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes()
432 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
481 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput()
H A DRegAllocFast.cpp326 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
430 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
487 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in reload()
756 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtReg()
851 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtRegUndef()
982 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in useVirtReg()
1086 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts()
1089 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx); in addRegClassDefCounts()
1100 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx); in addRegClassDefCounts()
1220 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in allocateInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp497 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || in getAVOperandEncoding()
498 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || in getAVOperandEncoding()
499 MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || in getAVOperandEncoding()
500 MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || in getAVOperandEncoding()
501 MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || in getAVOperandEncoding()
502 MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || in getAVOperandEncoding()
503 MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) || in getAVOperandEncoding()
504 MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) || in getAVOperandEncoding()
505 MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) || in getAVOperandEncoding()
506 MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg)) in getAVOperandEncoding()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp146 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
148 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
150 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
152 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
154 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
156 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
158 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
160 assert(RBGPR.covers(*TRI.getRegClass( in ARMRegisterBankInfo()
163 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
H A DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
270 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
271 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
514 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
515 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
531 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
537 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
635 MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg())); in runOnInstruction()
/llvm-project-15.0.7/llvm/test/TableGen/
H A DAsmPredicateCombiningRISCV.td63 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
70 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
76 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
84 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
91 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TileConfig.cpp118 unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs(); in INITIALIZE_PASS_DEPENDENCY()
124 if (MRI.getRegClass(VirtReg)->getID() != X86::TILERegClassID) in INITIALIZE_PASS_DEPENDENCY()
179 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY()
H A DX86InstructionSelector.cpp129 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
200 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, in getRegClass() function in X86InstructionSelector
203 return getRegClass(Ty, RegBank); in getRegClass()
251 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
281 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
730 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
731 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
816 MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI)); in selectZext()
859 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext()
860 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectAnyext()
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H A DX86FastPreTileConfig.cpp127 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
208 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
222 const TargetRegisterClass &RC = *MRI->getRegClass(OrigReg); in reload()
282 MRI->getRegClass(Reg)->getID() == X86::TILERegClassID) in isTileDef()
428 MRI->getRegClass(MO.getReg())->getID() == X86::TILERegClassID) in isTileRegDef()
528 MRI->getRegClass(Reg)->getID() == X86::TILERegClassID) in configBasicBlock()
670 if (MRI->getRegClass(VirtReg)->getID() == X86::TILERegClassID) { in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNPreRAOptimizations.cpp91 bool IsAGPRDst = TRI->isAGPRClass(MRI->getRegClass(Reg)); in processReg()
113 bool IsAGPRSrc = TRI->isAGPRClass(MRI->getRegClass(SrcReg)); in processReg()
231 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in runOnMachineFunction()
H A DSIFixSGPRCopies.cpp142 if (TRI->hasVectorRegisters(MRI.getRegClass(MO.getReg()))) in hasVectorOperands()
156 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
163 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
231 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
276 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
611 TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID)); in runOnMachineFunction()
699 DstRC = MRI->getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
700 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
701 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
819 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg()); in processPHINode()
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H A DSIInstrInfo.cpp1132 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in insertVectorSelect()
2732 if (MRI.getRegClass(FalseReg) != RC) in canInsertSelect()
2747 if (MRI.getRegClass(FalseReg) != RC) in canInsertSelect()
4799 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
4842 return MRI.getRegClass(Reg); in getOpRegClass()
5751 MRI.getRegClass(MI.getOperand(i).getReg()); in legalizeOperands()
6507 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in lowerSelect()
6720 MRI.getRegClass(Src0.getReg()) : in splitScalar64BitUnaryOp()
6850 MRI.getRegClass(Src0.getReg()) : in splitScalar64BitBinaryOp()
6855 MRI.getRegClass(Src1.getReg()) : in splitScalar64BitBinaryOp()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
133 MRI.getRegClass(AddendSrcReg)) in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
238 MRI.getRegClass(OldFMAReg))) in processBlock()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp220 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
430 TII->getRegClass(TII->get(Opcode.first), 0, TRI, *MF); in splitTwoPartImm()
432 TII->getRegClass(TII->get(Opcode.first), 1, TRI, *MF); in splitTwoPartImm()
436 : TII->getRegClass(TII->get(Opcode.second), 0, TRI, *MF); in splitTwoPartImm()
440 : TII->getRegClass(TII->get(Opcode.second), 1, TRI, *MF); in splitTwoPartImm()
456 MRI->constrainRegClass(NewDstReg, MRI->getRegClass(DstReg)); in splitTwoPartImm()
H A DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp140 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
335 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
434 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); in convertToPredForm()
478 if (MRI->getRegClass(DR.R) != PredRC) in eliminatePredCopies()
480 if (MRI->getRegClass(SR.R) != PredRC) in eliminatePredCopies()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp135 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
160 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
207 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
236 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
317 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
452 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
519 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
576 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
617 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); in EmitCopyToRegClassNode()
634 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); in EmitRegSequence()
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