1068   const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);  in materializeImmediate()
1132     RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in insertVectorSelect()
1133   assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&  in insertVectorSelect()
2731     const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);  in canInsertSelect()
2732     if (MRI.getRegClass(FalseReg) != RC)  in canInsertSelect()
2746     const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);  in canInsertSelect()
2747     if (MRI.getRegClass(FalseReg) != RC)  in canInsertSelect()
2775   const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);  in insertSelect()
2992       if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))  in FoldImmediate()
2995       if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))  in FoldImmediate()
3056                      RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))  in FoldImmediate()
3072                     RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))  in FoldImmediate()
3914     return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));  in usesConstantBus()
4124       const TargetRegisterClass *RC = RI.getRegClass(RegClass);  in verifyInstruction()
4639       const TargetRegisterClass &RC = *MRI.getRegClass(Reg);  in verifyInstruction()
4799   return RI.getProperlyAlignedRC(RI.getRegClass(RCID));  in adjustAllocatableRegClass()
4802 const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,  in getRegClass()  function in SIInstrInfo
4842       return MRI.getRegClass(Reg);  in getOpRegClass()
4856   const TargetRegisterClass *RC = RI.getRegClass(RCID);  in legalizeOpWithMove()
4946   const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);  in isLegalRegOperand()
4950   const TargetRegisterClass *RC = MRI.getRegClass(Reg);  in isLegalRegOperand()
4983       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;  in isOperandLegal()
5198     if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {  in legalizeOperandsVOP3()
5204     if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {  in legalizeOperandsVOP3()
5270   const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);  in readlaneVGPRToSGPR()
5318   if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {  in legalizeOperandsSMRD()
5323   if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {  in legalizeOperandsSMRD()
5418   if (!SAddr || RI.isSGPRClass(MRI.getRegClass(SAddr->getReg())))  in legalizeOperandsFLAT()
5488   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in emitLoadSRsrcFromVGPRLoop()
5547   auto SRsrcRC = TRI->getEquivalentSGPRClass(MRI.getRegClass(VRsrc));  in emitLoadSRsrcFromVGPRLoop()
5602   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in loadSRsrcFromVGPR()
5751           MRI.getRegClass(MI.getOperand(i).getReg());  in legalizeOperands()
5812         const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());  in legalizeOperands()
5830     const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);  in legalizeOperands()
5831     const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);  in legalizeOperands()
5843     if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))  in legalizeOperands()
5856     if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg())))  in legalizeOperands()
5860     if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg())))  in legalizeOperands()
5869     if (!RI.isSGPRClass(MRI.getRegClass(Dest->getReg()))) {  in legalizeOperands()
5900     if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),  in legalizeOperands()
5901                              RI.getRegClass(RsrcRC))) {  in legalizeOperands()
5930       const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in legalizeOperands()
6241       const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in moveToVALU()
6253           MRI.getRegClass(Inst.getOperand(0).getReg())));  in moveToVALU()
6281           RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg()));  in moveToVALU()
6507       RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in lowerSelect()
6611                       RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));  in lowerScalarXnor()
6613                       RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));  in lowerScalarXnor()
6720     MRI.getRegClass(Src0.getReg()) :  in splitScalar64BitUnaryOp()
6728   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());  in splitScalar64BitUnaryOp()
6770   const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in splitScalar64BitAddSub()
6785   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());  in splitScalar64BitAddSub()
6786   const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());  in splitScalar64BitAddSub()
6850     MRI.getRegClass(Src0.getReg()) :  in splitScalar64BitBinaryOp()
6855     MRI.getRegClass(Src1.getReg()) :  in splitScalar64BitBinaryOp()
6869   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());  in splitScalar64BitBinaryOp()
6912   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());  in splitScalar64BitXnor()
6954     MRI.getRegClass(Src.getReg()) :  in splitScalar64BitBCNT()
7295     const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);  in findUsedSGPR()
7302     const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);  in findUsedSGPR()
7764   return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);  in isBufferSMRD()
8202       const TargetRegisterClass *RC = MRI.getRegClass(VirtReg);  in foldMemoryOperandImpl()