Searched refs:getPhysRegClass (Results 1 – 9 of 9) sorted by relevance
184 const TargetRegisterClass *getPhysRegClass(MCRegister Reg) const;
157 : TRI.getPhysRegClass(SrcReg); in getCopyRegClasses()164 : TRI.getPhysRegClass(DstReg); in getCopyRegClasses()
125 const TargetRegisterClass *RC = TRI.getPhysRegClass(SuperReg); in SGPRSpillBuilder()2603 SIRegisterInfo::getPhysRegClass(MCRegister Reg) const { in getPhysRegClass() function in SIRegisterInfo2677 RC = getPhysRegClass(Reg); in isSGPRReg()2814 return Reg.isVirtual() ? MRI.getRegClass(Reg) : getPhysRegClass(Reg); in getRegClassForReg()3017 assert(getRegSizeInBits(*getPhysRegClass(Reg)) <= 32); in get32BitRegister()
610 TRI->hasVectorRegisters(TRI->getPhysRegClass(Reg))) { in scanInstructions()1455 Reg.isVirtual() ? MRI->getRegClass(Reg) : TRI->getPhysRegClass(Reg); in lowerCopyInstrs()
481 const TargetRegisterClass *RC = TRI.getPhysRegClass(VGPR); in allocateWWMReservedSpillSlots()
1194 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) { in fixSMEMtoVectorWriteHazards()1275 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) in fixVcmpxExecWARHazard()
718 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg); in copyPhysReg()724 (RI.getRegSizeInBits(*RI.getPhysRegClass(SrcReg)) == 16))) { in copyPhysReg()736 RC = RI.getPhysRegClass(DestReg); in copyPhysReg()926 const TargetRegisterClass *SrcRC = RI.getPhysRegClass(SrcReg); in copyPhysReg()3053 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) || in FoldImmediate()3070 RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) || in FoldImmediate()4843 return RI.getPhysRegClass(Reg); in getOpRegClass()
370 return TRI->getPhysRegClass(Reg); in getOperandRegClass()1444 TRI.getPhysRegClass(cast<RegisterSDNode>(Val.getOperand(1))->getReg()); in IsCopyFromSGPR()
12189 Ret.second = TRI->getPhysRegClass(Ret.first); in getRegForInlineAsmConstraint()