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Searched refs:getNOT (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECustomDAG.cpp419 return DAG.getNOT(DL, Res, Res.getValueType()); in getConstantMask()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1562 SDValue New = TLO.DAG.getNOT(dl, Op0, VT); in SimplifyDemandedBits()
3734 SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT); in foldSetCCWithAnd()
4995 N0 = DAG.getNOT(dl, Temp, OpVT); in SimplifySetCC()
5004 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC()
5011 Temp = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC()
5018 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC()
5025 Temp = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC()
7173 Z = DAG.getNOT(DL, Z, ShVT); in expandFunnelShift()
7968 Op = DAG.getNOT(dl, Op, VT); in expandCTLZ()
8010 ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT), in expandCTTZ()
[all …]
H A DLegalizeVectorOps.cpp968 SDValue NotMask = DAG.getNOT(DL, Mask, MaskTy); in ExpandSELECT()
1231 SDValue NotMask = DAG.getNOT(DL, Mask, VT); in ExpandVSELECT()
H A DDAGCombiner.cpp5521 SDValue Mask = DAG.getNOT(DL, Diff, OpVT); in foldLogicOfSetCCs()
8375 SDValue NotX = DAG.getNOT(DL, X, VT); in unfoldMaskedMerge()
8377 SDValue NotLHS = DAG.getNOT(DL, LHS, VT); in unfoldMaskedMerge()
8389 SDValue NotY = DAG.getNOT(DL, Y, VT); in unfoldMaskedMerge()
8391 SDValue NotRHS = DAG.getNOT(DL, RHS, VT); in unfoldMaskedMerge()
8396 SDValue NotM = DAG.getNOT(DL, M, VT); in unfoldMaskedMerge()
8546 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT); in visitXOR()
10331 SDValue Not = DAG.getNOT(DL, Sra, VT); in foldVSelectToSignBitSplatMask()
11836 SDValue NotX = DAG.getNOT(DL, X, VT); in foldExtendedSignBitTest()
23929 Shift = DAG.getNOT(DL, Shift, AType); in foldSelectCCToShiftAnd()
[all …]
H A DSelectionDAG.cpp1419 SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) { in getNOT() function in SelectionDAG
5386 return getNOT(DL, Operand, Operand.getValueType()); in getNode()
5995 return getNode(ISD::AND, DL, VT, N1, getNOT(DL, N2, VT)); in getNode()
H A DLegalizeDAG.cpp3291 Tmp1 = DAG.getNOT(dl, Node->getOperand(1), VT); in ExpandNode()
H A DLegalizeIntegerTypes.cpp4037 SignsMatch = DAG.getNOT(dl, SignsMatch, VT); in ExpandIntRes_SADDSUBO()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp1519 DAG.getNOT(DL, Bit, ResTy)); in lowerMSABitClear()
2080 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN()
2086 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp2086 Res = DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
2202 return DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1065 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
H A DAMDGPUISelLowering.cpp2098 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
H A DSIISelLowering.cpp5742 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h906 SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp24571 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
24654 Result = DAG.getNOT(dl, Result, MVT::v4i32); in LowerVSETCC()
24677 Result = DAG.getNOT(dl, Result, MVT::v4i32); in LowerVSETCC()
24697 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
25227 Shift = DAG.getNOT(DL, Shift, VT); in LowerSELECT()
25303 return DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
44348 Cond = DAG.getNOT(DL, Cond, MVT::i1); in combineSelectOfTwoConstants()
44902 SDValue CondNew = DAG.getNOT(DL, Cond, CondVT); in combineSelect()
50934 return DAG.getBitcast(VT, DAG.getNOT(SDLoc(N), N0.getOperand(0), in combineXor()
52178 return DAG.getNOT(DL, Op0.getOperand(0), VT); in combineSetCC()
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H A DX86ISelDAGToDAG.cpp909 Complement = CurDAG->getNOT(dl, Complement, VT); in PreprocessISelDAG()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4106 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy)); in LowerINTRINSIC_WO_CHAIN()
6725 Merged = DAG.getNOT(dl, Merged, CmpVT); in LowerVSETCC()
6767 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
6779 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
6821 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
6855 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12010 return DAG.getNOT(dl, Fcmeq, VT); in EmitVectorComparison()
12054 return DAG.getNOT(dl, Cmeq, VT); in EmitVectorComparison()
12151 Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType()); in LowerVSETCC()
19451 SDValue InvMask = DAG.getNOT(DL, Mask, VT); in performBSPExpandForSVE()