Searched refs:getMaxNumSGPRs (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSubtarget.h | 1130 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const { in getMaxNumSGPRs() function
1131 return AMDGPU::IsaInfo::getMaxNumSGPRs(this, WavesPerEU, Addressable); in getMaxNumSGPRs()
1160 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
1170 unsigned getMaxNumSGPRs(const Function &F) const;
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| H A D | AMDGPUSubtarget.cpp | 681 unsigned MaxNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, false); in getBaseMaxNumSGPRs()
682 unsigned MaxAddressableNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, true); in getBaseMaxNumSGPRs()
707 if (Requested && Requested > getMaxNumSGPRs(WavesPerEU.first, false)) in getBaseMaxNumSGPRs()
723 unsigned GCNSubtarget::getMaxNumSGPRs(const MachineFunction &MF) const { in getMaxNumSGPRs() function in GCNSubtarget
753 unsigned GCNSubtarget::getMaxNumSGPRs(const Function &F) const { in getMaxNumSGPRs() function in GCNSubtarget
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| H A D | SIRegisterInfo.cpp | 540 unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4; in reservedPrivateSegmentBufferReg()
605 unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF); in getReservedRegs()
2868 return std::min(ST.getMaxNumSGPRs(Occupancy, true), ST.getMaxNumSGPRs(MF)); in getRegPressureLimit()
3084 ST.getMaxNumSGPRs(MF) / 4); in getAllSGPR128()
3090 ST.getMaxNumSGPRs(MF) / 2); in getAllSGPR64()
3095 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF)); in getAllSGPR32()
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| H A D | GCNSchedStrategy.cpp | 61 std::min(ST.getMaxNumSGPRs(TargetOccupancy, true), SGPRExcessLimit); in initialize()
728 unsigned MaxSGPRs = ST.getMaxNumSGPRs(MF); in checkScheduling()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 237 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
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| H A D | AMDGPUBaseInfo.cpp | 773 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, in getMaxNumSGPRs() function
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