| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 129 Res.addDefToMIB(*getMRI(), MIB); in buildDynStackAlloc() 139 Res.addDefToMIB(*getMRI(), MIB); in buildFrameIndex() 184 Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch"); in buildPtrAdd() 201 Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0)); in materializePtrAdd() 512 assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI())); in buildExtOrTrunc() 1033 DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()), in buildInstr() 1034 SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI())); in buildInstr() 1124 assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) && in buildInstr() 1257 assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) && in buildInstr() 1258 (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) && in buildInstr() [all …]
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| H A D | CSEMIRBuilder.cpp | 80 B.addNodeIDRegType(Op.getLLTTy(*getMRI())); in profileDstOp() 198 LLT SrcTy = SrcOps[0].getLLTTy(*getMRI()); in buildInstr() 207 Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI()); in buildInstr() 234 Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI())) in buildInstr() 255 Opc, DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getReg(), *getMRI())) in buildInstr() 269 LLT VecTy = DstOps[0].getLLTTy(*getMRI()); in buildInstr() 289 GISelInstProfileBuilder ProfBuilder(ID, *getMRI()); in buildInstr() 310 LLT Ty = Res.getLLTTy(*getMRI()); in buildConstant() 315 GISelInstProfileBuilder ProfBuilder(ID, *getMRI()); in buildConstant() 337 LLT Ty = Res.getLLTTy(*getMRI()); in buildFConstant() [all …]
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| H A D | InlineAsmLowering.cpp | 240 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); in buildAnyextOrCopy() 283 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); in lowerInlineAsm()
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| H A D | CallLowering.cpp | 277 MachineRegisterInfo &MRI = *B.getMRI(); in mergeVectorRegsToResultRegs() 324 MachineRegisterInfo &MRI = *B.getMRI(); in buildCopyFromRegs() 499 MachineRegisterInfo &MRI = *B.getMRI(); in buildCopyToRegs()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVCallLowering.cpp | 210 auto MRI = MIRBuilder.getMRI(); in lowerFormalArguments() 299 {MIRBuilder.getMRI()->createGenericVirtualRegister(LLT::scalar(32))}); in lowerCall() 309 ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass); in lowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCCallLowering.cpp | 122 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64GlobalISelUtils.cpp | 67 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in tryEmitBZero()
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| H A D | AArch64InstructionSelector.cpp | 1081 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitSelect() 1497 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitTestBit() 1570 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitCBZ() 1617 MachineRegisterInfo &MRI = *MIB.getMRI(); in tryOptCompareBranchFedByICmp() 4711 auto &MRI = *MIRBuilder.getMRI(); in emitCSINC() 4820 auto &MRI = *MIB.getMRI(); in emitConditionalComparison() 4853 auto &MRI = *MIB.getMRI(); in emitConjunctionRec() 4968 *MIB.getMRI())) in emitConjunction() 4986 MachineRegisterInfo &MRI = *MIB.getMRI(); in tryOptSelect() 5572 auto &MRI = *MIB.getMRI(); in selectVectorLoadIntrinsic() [all …]
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| H A D | AArch64LegalizerInfo.cpp | 828 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in legalizeCustom() 896 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in legalizeVectorTrunc() 1392 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in legalizeCTTZ()
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| H A D | AArch64PreLegalizerCombiner.cpp | 256 auto &MRI = *B.getMRI(); in tryToSimplifyUADDO()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 1738 MachineRegisterInfo &MRI = *B.getMRI(); in legalizeCustom() 2628 MachineRegisterInfo &MRI = *B.getMRI(); in legalizeLoad() 2758 LLT Ty = B.getMRI()->getType(Dst); in legalizeFlog() 2774 LLT Ty = B.getMRI()->getType(Dst); in legalizeFExp() 2789 LLT Ty = B.getMRI()->getType(Dst); in legalizeFPow() 3154 MachineRegisterInfo &MRI = *B.getMRI(); in legalizeMul() 4255 MachineRegisterInfo &MRI = *B.getMRI(); in splitBufferOffsets() 4384 MachineRegisterInfo *MRI = B.getMRI(); in fixStoreSourceType() 4875 MachineRegisterInfo *MRI = B.getMRI(); in legalizeImageIntrinsic() 5222 LLT Ty = B.getMRI()->getType(Dst); in legalizeSBufferLoad() [all …]
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| H A D | AMDGPURegisterBankInfo.cpp | 645 MachineRegisterInfo *MRI = B.getMRI(); in split64BitValueForMapping() 1253 MachineRegisterInfo *MRI = B.getMRI(); in setBufferOffsets() 1328 B.getMRI()->setRegBank(SOffsetReg, AMDGPU::SGPRRegBank); in setBufferOffsets() 1335 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyMappingSBufferLoad() 1390 B.getMRI()->setRegBank(VIndex, AMDGPU::VGPRRegBank); in applyMappingSBufferLoad() 1454 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyMappingBFE() 1561 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyMappingMAD_64_32() 1847 MachineRegisterInfo &MRI = *B.getMRI(); in buildVCopy() 1884 MachineRegisterInfo &MRI = *B.getMRI(); in reinsertVectorIndexAdd() 1916 B.getMRI()->setRegBank(ShiftAmt.getReg(0), RegBank); in extendLow32IntoHigh32() [all …]
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| H A D | SIPeepholeSDWA.cpp | 102 MachineRegisterInfo *getMRI() const { in getMRI() function in __anona3dad2400111::SDWAOperand 332 MachineOperand *PotentialMO = findSingleRegUse(getReplacedOperand(), getMRI()); in potentialToConvert() 416 MachineRegisterInfo *MRI = getMRI(); in potentialToConvert() 470 getMRI()->clearKillFlags(MO.getReg()); in convertToSDWA()
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| H A D | AMDGPUPreLegalizerCombiner.cpp | 44 : B(B), MF(B.getMF()), MRI(*B.getMRI()), Helper(Helper){}; in AMDGPUPreLegalizerCombinerHelper()
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| H A D | SIMachineScheduler.h | 452 MachineRegisterInfo *getMRI() { return &MRI; } in getMRI() function
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| H A D | AMDGPURegBankCombiner.cpp | 47 : B(B), MF(B.getMF()), MRI(*B.getMRI()), in AMDGPURegBankCombinerHelper()
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| H A D | AMDGPUPostLegalizerCombiner.cpp | 44 : B(B), MF(B.getMF()), MRI(*B.getMRI()), Helper(Helper){}; in AMDGPUPostLegalizerCombinerHelper()
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| H A D | SIMachineScheduler.cpp | 311 MachineRegisterInfo *MRI = DAG->getMRI(); in initRegPressure() 1712 PSetIterator PSetI = DAG->getMRI()->getPressureSets(Reg); in checkRegUsageImpact() 1722 PSetIterator PSetI = DAG->getMRI()->getPressureSets(Reg); in checkRegUsageImpact()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 287 MachineRegisterInfo *getMRI() { return State.MRI; } in getMRI() function 288 const MachineRegisterInfo *getMRI() const { return State.MRI; } in getMRI() function 1622 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1); in buildNot() 1630 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0); in buildNeg()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 334 MachineRegisterInfo &getMRI() const { return MRI; } in getMRI() function
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 130 MIRBuilder.getMRI()->addLiveIn(PhysReg); in assignValueToReg()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 217 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 356 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
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| H A D | ARMLegalizerInfo.cpp | 370 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in legalizeCustom()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsLegalizerInfo.cpp | 337 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in legalizeCustom()
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