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Searched refs:getLatency (Results 1 – 25 of 26) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DScheduleDAG.cpp85 dbgs() << " Latency=" << getLatency(); in dump()
91 dbgs() << " Latency=" << getLatency(); in dump()
94 dbgs() << " Latency=" << getLatency(); in dump()
117 if (PredDep.getLatency() < D.getLatency()) { in addPred()
124 SuccDep.setLatency(D.getLatency()); in addPred()
128 PredDep.setLatency(D.getLatency()); in addPred()
168 if (P.getLatency() != 0) { in addPred()
211 if (P.getLatency() != 0) { in removePred()
276 PredSU->Depth + PredDep.getLatency()); in ComputeDepth()
307 SuccSU->Height + SuccDep.getLatency()); in ComputeHeight()
H A DLatencyPriorityQueue.cpp36 unsigned LHSLatency = PQ->getLatency(LHSNum); in operator ()()
37 unsigned RHSLatency = PQ->getLatency(RHSNum); in operator ()()
H A DVLIWMachineScheduler.cpp97 if (S.getSUnit() == SUu && S.getLatency() > 0) in hasDependence()
313 unsigned MinLatency = PI.getLatency(); in releaseTopNode()
331 unsigned MinLatency = I->getLatency(); in releaseBottomNode()
712 PI.getLatency() == 0 && in SchedulingCost()
721 SI.getLatency() == 0 && in SchedulingCost()
737 if (PI.getLatency() > 0 && in SchedulingCost()
745 if (SI.getLatency() > 0 && in SchedulingCost()
H A DMachineCombiner.cpp99 unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
268 unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot, in getLatency() function in MachineCombiner
344 NewRootLatency += getLatency(&MI, NewRoot, BlockTrace); in getLatenciesForInstrSequences()
H A DMachinePipeliner.cpp1177 unsigned Delay = Nodes.getLatency(); in calculateRecMII()
1205 unsigned Lat = D.getLatency(); in swapAntiDependences()
1454 if (P.getLatency() == 0) in computeNodeFunctions()
1459 asap = std::max(asap, (int)(getASAP(pred) + P.getLatency() - in computeNodeFunctions()
1476 if (S.getLatency() == 0) in computeNodeFunctions()
1481 alap = std::min(alap, (int)(getALAP(succ) - S.getLatency() + in computeNodeFunctions()
2486 int EarlyStart = cycle + Dep.getLatency() - in computeStart()
2494 int LateStart = cycle - Dep.getLatency() + in computeStart()
2510 int LateStart = cycle - Dep.getLatency() + in computeStart()
2518 int EarlyStart = cycle + Dep.getLatency() - in computeStart()
H A DCriticalAntiDepBreaker.cpp146 unsigned PredLatency = P.getLatency(); in CriticalPathStep()
H A DMachineScheduler.cpp657 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
658 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
694 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
695 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency(); in releasePred()
H A DAggressiveAntiDepBreaker.cpp277 unsigned PredLatency = Pred.getLatency(); in CriticalPathStep()
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstruction.cpp57 CyclesLeft = getLatency(); in onInstructionIssued()
126 dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID " in dump()
178 CyclesLeft = getLatency(); in execute()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonHazardRecognizer.cpp149 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
164 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
H A DHexagonSubtarget.cpp287 if (SI.getKind() != SDep::Order || SI.getLatency() != 0) in apply()
523 int Latency = Dep.getLatency(); in adjustSchedDependency()
613 F->setLatency(I.getLatency()); in restoreLatency()
637 if (I.isAssignedRegDep() && I.getLatency() == 0 && in getZeroLatency()
H A DHexagonVLIWPacketizer.cpp1922 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) || in calcStall()
1932 if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1) in calcStall()
1933 return Pred.getLatency(); in calcStall()
/llvm-project-15.0.7/mlir/lib/Dialect/SCF/TransformOps/
H A DSCFTransformOps.cpp159 auto getLatency = [&](Operation *op) -> unsigned { in loopScheduling() local
175 earlyCycle = std::max(earlyCycle, opCycles[def] + getLatency(def)); in loopScheduling()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DLatencyPriorityQueue.h68 unsigned getLatency(unsigned NodeNum) const { in getLatency() function
H A DResourcePriorityQueue.h93 unsigned getLatency(unsigned NodeNum) const { in getLatency() function
H A DMachinePipeliner.h342 unsigned CurLatency = Succ.getLatency(); in NodeSet()
392 unsigned getLatency() { return Latency; } in getLatency() function
H A DScheduleDAG.h142 unsigned getLatency() const { in getLatency() function
/llvm-project-15.0.7/llvm/include/llvm/MCA/
H A DInstruction.h263 unsigned getLatency() const { return WD->Latency; } in getLatency() function
295 return !CyclesLeft || CyclesLeft < getLatency(); in isReady()
541 unsigned getLatency() const { return Desc.MaxLatency; } in getLatency() function
/llvm-project-15.0.7/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp194 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) { in getLatency() function
231 int Latency = getLatency(DC, Inst); in emitLatency()
/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp89 unsigned FirstWBCycle = IR.getInstruction()->getLatency(); in findFirstWriteBackCycle()
93 CyclesLeft = WS.getLatency(); in findFirstWriteBackCycle()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGVLIW.cpp124 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); in releaseSucc()
H A DResourcePriorityQueue.cpp189 unsigned LHSLatency = PQ->getLatency(LHSNum); in operator ()()
190 unsigned RHSLatency = PQ->getLatency(RHSNum); in operator ()()
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp296 if (OtherWS->getLatency() > WS.getLatency()) { in addRegisterWrite()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNILPSched.cpp282 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge.getLatency()); in releasePredecessors()
H A DAMDGPUSubtarget.cpp832 } else if (Dep.getLatency() == 0 && Dep.getReg() == AMDGPU::VCC_LO) { in adjustSchedDependency()

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