| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 204 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI); in computeOperandLatency()
278 return TII->getInstrLatency(&InstrItins, *MI); in computeInstrLatency()
|
| H A D | TargetInstrInfo.cpp | 1104 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in TargetInstrInfo
1150 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in TargetInstrInfo
|
| H A D | TwoAddressInstructionPass.cpp | 849 if (TII->getInstrLatency(InstrItins, *MI) > 1) in rescheduleMIBelowKill()
983 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist)) in isDefTooClose()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 207 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
|
| H A D | AMDGPUSubtarget.cpp | 815 Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *I); in adjustSchedDependency()
825 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *DefI); in adjustSchedDependency()
|
| H A D | SIInstrInfo.h | 1166 unsigned getInstrLatency(const InstrItineraryData *ItinData,
|
| H A D | R600InstrInfo.cpp | 983 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in R600InstrInfo
|
| H A D | SIInstrInfo.cpp | 8216 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in SIInstrInfo
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 454 unsigned getInstrLatency(const InstrItineraryData *ItinData,
458 int getInstrLatency(const InstrItineraryData *ItinData,
|
| H A D | ARMBaseInstrInfo.cpp | 4407 unsigned Latency = getInstrLatency(ItinData, DefMI); in getOperandLatencyImpl()
4729 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in ARMBaseInstrInfo
4744 Latency += getInstrLatency(ItinData, *I, PredCost); in getInstrLatency()
4780 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in ARMBaseInstrInfo
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1620 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1626 virtual int getInstrLatency(const InstrItineraryData *ItinData,
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 279 unsigned getInstrLatency(const InstrItineraryData *ItinData,
|
| H A D | HexagonInstrInfo.cpp | 1961 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in HexagonInstrInfo
4273 return getInstrLatency(ItinData, MI); in getInstrTimingClassLatency()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 409 unsigned getInstrLatency(const InstrItineraryData *ItinData,
|
| H A D | PPCInstrInfo.cpp | 136 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in PPCInstrInfo
140 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency()
192 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 641 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
|