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Searched refs:getDesc (Results 1 – 25 of 166) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h352 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
360 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
376 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
490 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
522 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
553 return MI.getDesc().TSFlags & SIInstrFlags::EXP; in isEXP()
595 return MI.getDesc().TSFlags & SIInstrFlags::WQM; in isWQM()
627 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
758 return MI.getDesc().TSFlags & ClampFlags; in getClampMask()
823 if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) { in isInlineConstant()
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H A DSIPostRABundler.cpp110 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in isBundleCandidate()
116 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in canBundle()
120 ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) && in canBundle()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp243 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
250 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
336 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
342 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
348 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
558 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) || in isConstExtended()
560 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch())) in isConstExtended()
580 return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() && in isCanon()
933 MCInstrDesc const &Desc = getDesc(MCII, MCI); in predicateInfo()
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H A DHexagonShuffler.cpp130 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
198 MCInst const &Inst = ISJ.getDesc(); in restrictSlot1AOK()
230 MCInst const &Inst = ISJ.getDesc(); in restrictNoSlot1Store()
231 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store()
365 MCInst const &ID = ISJ->getDesc(); in restrictStoreLoadOrder()
372 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
405 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { in restrictStoreLoadOrder()
456 MCInst const &ID = ISJ->getDesc(); in GetPacketSummary()
501 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in GetPacketSummary()
549 if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) in GetPacketSummary()
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H A DHexagonMCShuffler.cpp41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
85 MCInst const &MI = I.getDesc(); in copyTo()
H A DHexagonMCChecker.cpp93 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
432 bool Branch = HexagonMCInstrInfo::getDesc(MCII, ConsumerInst).isBranch(); in checkNewValues()
480 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, *ProducerInst); in checkNewValues()
537 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
554 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
571 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in registerProducer()
597 HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) { in checkRegisterCurDefs()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp38 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
65 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
66 J->getDesc().isIndirectBranch()) { in analyzeBranch()
82 if (I->getDesc().isIndirectBranch()) in analyzeBranch()
96 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { in analyzeBranch()
103 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
121 if (!I->getDesc().isUnconditionalBranch() && in removeBranch()
122 !I->getDesc().isConditionalBranch()) in removeBranch()
135 if (!I->getDesc().isConditionalBranch()) in removeBranch()
147 assert(MI.getDesc().isBranch() && "Unexpected opcode!"); in getBranchDestBlock()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetSchedule.cpp109 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
134 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
197 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
241 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
326 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput()
H A DExecutionDomainFix.cpp237 const MCInstrDesc &MCID = MI->getDesc(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
260 e = mi->getDesc().getNumOperands(); in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
291 e = mi->getDesc().getNumOperands(); in visitSoftInstr()
H A DPeepholeOptimizer.cpp890 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1190 assert(MI.getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1336 const MCInstrDesc &MCID = MI.getDesc(); in isLoadFoldable()
1355 const MCInstrDesc &MCID = MI.getDesc(); in isMoveImmediate()
1376 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) { in foldImmediate()
1531 if (MI.getDesc().getNumDefs() != 1) in findTargetRecurrence()
1770 const MCInstrDesc &MIDesc = MI->getDesc(); in runOnMachineFunction()
1852 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
2068 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2069 Def->getDesc().isVariadic())) || in getNextSourceImpl()
H A DTargetInstrInfo.cpp168 const MCInstrDesc &MCID = MI.getDesc(); in commuteInstructionImpl()
205 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
210 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
300 const MCInstrDesc &MCID = MI.getDesc(); in findCommutedOpIndices()
336 const MCInstrDesc &MCID = MI.getDesc(); in PredicateInstruction()
1124 unsigned Class = MI.getDesc().getSchedClass(); in getNumMicroOps()
1158 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1168 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()
1261 unsigned DefClass = DefMI.getDesc().getSchedClass(); in getOperandLatency()
1262 unsigned UseClass = UseMI.getDesc().getSchedClass(); in getOperandLatency()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86DiscriminateMemOps.cpp114 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
130 if (X86II::getMemoryOperandNo(MI.getDesc().TSFlags) < 0) in runOnMachineFunction()
132 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
/llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/
H A DReduceRegisterUses.cpp31 MI.getDesc().getNumImplicitDefs() + in removeUsesFromFunction()
32 MI.getDesc().getNumImplicitUses(); in removeUsesFromFunction()
H A DReduceRegisterDefs.cpp42 MI.getDesc().getNumImplicitDefs() + in removeDefsFromFunction()
43 MI.getDesc().getNumImplicitUses(); in removeDefsFromFunction()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp31 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
52 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
55 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
112 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset()
H A DARMBaseRegisterInfo.cpp532 const MCInstrDesc &Desc = MI->getDesc(); in getFrameIndexInstrOffset()
724 const MCInstrDesc &Desc = MI->getDesc(); in isFrameOffsetLegal()
840 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || in eliminateFrameIndex()
841 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6 || in eliminateFrameIndex()
842 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7 || in eliminateFrameIndex()
843 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7s2 || in eliminateFrameIndex()
844 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == in eliminateFrameIndex()
854 const MCInstrDesc &MCID = MI.getDesc(); in eliminateFrameIndex()
/llvm-project-15.0.7/llvm/lib/Support/
H A DStatistic.cpp149 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0; in sort()
196 MaxDebugTypeLen, Stat->getDebugType(), Stat->getDesc()); in PrintStatistics()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp74 const InstrDesc &D = IS->getDesc(); in issueInstructionImpl()
199 uint64_t BusyResourceMask = Resources->checkAvailability(IS.getDesc()); in select()
253 if (Resources->checkAvailability(IS.getDesc())) in analyzeDataDependencies()
291 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in mustIssueImmediately()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp236 uint64_t TSFlags = MBBI->getDesc().TSFlags; in isConvertibleToVMV_V_V()
768 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
835 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
836 J->getDesc().isIndirectBranch()) { in analyzeBranch()
852 if (I->getDesc().isIndirectBranch()) in analyzeBranch()
873 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
891 if (!I->getDesc().isUnconditionalBranch() && in removeBranch()
892 !I->getDesc().isConditionalBranch()) in removeBranch()
905 if (!I->getDesc().isConditionalBranch()) in removeBranch()
1422 uint64_t TSFlags = MI.getDesc().TSFlags; in createMIROperandComment()
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H A DRISCVInsertVSETVLI.cpp48 return RISCVII::getVLOpNum(MI.getDesc()); in getVLOpNum()
52 return RISCVII::getSEWOpNum(MI.getDesc()); in getSEWOpNum()
277 if (RISCVII::hasSEWOp(MI.getDesc().TSFlags)) { in isMaskRegOp()
368 uint64_t TSFlags = MI.getDesc().TSFlags; in getDemanded()
948 assert(Require == computeInfoForInstr(MI, MI.getDesc().TSFlags, MRI)); in needVSETVLI()
993 uint64_t TSFlags = MI.getDesc().TSFlags; in transferBefore()
1076 if (isVectorConfigInstr(MI) || RISCVII::hasSEWOp(MI.getDesc().TSFlags)) in computeVLVTYPEChanges()
1203 uint64_t TSFlags = MI.getDesc().TSFlags; in emitVSETVLIs()
1334 const uint64_t TSFlags = MI.getDesc().TSFlags; in doPRE()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1660 const uint64_t F = MI.getDesc().TSFlags; in isPredicated()
1749 if (!MI.getDesc().isPredicable()) in isPredicable()
2114 const uint64_t F = MI.getDesc().TSFlags; in isAccumulator()
2124 !MI.getDesc().mayStore() && in isComplex()
2138 const uint64_t F = MI.getDesc().TSFlags; in isConstExtended()
2197 if (!ProdMI.getDesc().getNumDefs()) in isDependent()
2276 const MCInstrDesc &MID = MI.getDesc(); in isExtendable()
2299 const uint64_t F = MI.getDesc().TSFlags; in isExtended()
3092 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) { in hasNonExtEquivalent()
4495 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) { in getNonExtOpcode()
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H A DHexagonOptAddrMode.cpp129 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
196 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
376 const MCInstrDesc &MID = MI->getDesc(); in getBaseOpPosition()
398 const MCInstrDesc &MID = MI->getDesc(); in getOffsetOpPosition()
425 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
520 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
702 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
749 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp580 return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0; in SafeInForbiddenSlot()
627 return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0; in HasForbiddenSlot()
669 return MI.getDesc().getSize(); in getInstSizeInBytes()
740 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
748 for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands(); in genInstrWithNewOpc()
757 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
776 const MCInstrDesc &MCID = MI.getDesc(); in findCommutedOpIndices()
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DLexicalScopesTest.cpp145 EXPECT_EQ(FuncScope->getDesc(), OurFunc); in TEST_F()
186 EXPECT_EQ(FuncScope->getDesc(), OurFunc); in TEST_F()
191 EXPECT_EQ(BlockScope->getDesc(), InBlockLoc->getScope()); in TEST_F()
230 EXPECT_EQ(InlinedScope->getDesc(), InlinedLoc.getScope()); in TEST_F()
241 EXPECT_EQ(AbstractScope.getDesc(), InlinedLoc.getScope()); in TEST_F()

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