1660   const uint64_t F = MI.getDesc().TSFlags;  in isPredicated()
1749   if (!MI.getDesc().isPredicable())  in isPredicable()
1809   if (MI.getDesc().isTerminator() || MI.isPosition())  in isSchedulingBoundary()
2114   const uint64_t F = MI.getDesc().TSFlags;  in isAccumulator()
2123   return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&  in isComplex()
2124          !MI.getDesc().mayStore() &&  in isComplex()
2125          MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&  in isComplex()
2126          MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&  in isComplex()
2138   const uint64_t F = MI.getDesc().TSFlags;  in isConstExtended()
2197   if (!ProdMI.getDesc().getNumDefs())  in isDependent()
2276   const MCInstrDesc &MID = MI.getDesc();  in isExtendable()
2299   const uint64_t F = MI.getDesc().TSFlags;  in isExtended()
2462   const uint64_t F = MI.getDesc().TSFlags;  in isNewValue()
2484   const uint64_t F = MI.getDesc().TSFlags;  in isNewValueStore()
2496   const uint64_t F = MI.getDesc().TSFlags;  in isOperandExtended()
2502   const uint64_t F = MI.getDesc().TSFlags;  in isPredicatedNew()
2514   const uint64_t F = MI.getDesc().TSFlags;  in isPredicatedTrue()
2630   const uint64_t F = MI.getDesc().TSFlags;  in isSolo()
2656   unsigned SchedClass = MI.getDesc().getSchedClass();  in isTC1()
2661   unsigned SchedClass = MI.getDesc().getSchedClass();  in isTC2()
2666   unsigned SchedClass = MI.getDesc().getSchedClass();  in isTC2Early()
2671   unsigned SchedClass = MI.getDesc().getSchedClass();  in isTC4x()
3092   if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {  in hasNonExtEquivalent()
3138   const uint64_t F = MI.getDesc().TSFlags;  in mayBeCurLoad()
3148   const uint64_t F = MI.getDesc().TSFlags;  in mayBeNewStore()
3243   const uint64_t F = MI.getDesc().TSFlags;  in getAddrMode()
3380   const uint64_t F = MI.getDesc().TSFlags;  in getCExtOpNum()
4277   return ItinData->getStageLatency(MI.getDesc().getSchedClass());  in getInstrTimingClassLatency()
4355   const uint64_t F = MI.getDesc().TSFlags;  in getMaxValue()
4386   const uint64_t F = MI.getDesc().TSFlags;  in isAddrModeWithOffset()
4409   const uint64_t F = MI.getDesc().TSFlags;  in isRestrictNoSlot1Store()
4454   const uint64_t F = MI.getDesc().TSFlags;  in getMemAccessSize()
4475   const uint64_t F = MI.getDesc().TSFlags;  in getMinValue()
4495   if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {  in getNonExtOpcode()
4548   unsigned Size = MI.getDesc().getSize();  in getSize()
4579   const uint64_t F = MI.getDesc().TSFlags;  in getType()
4585   const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());  in getUnits()
4652                       << "  Class: " << NewMI->getDesc().getSchedClass());  in genAllInsnTimingClasses()