236           uint64_t TSFlags = MBBI->getDesc().TSFlags;  in isConvertibleToVMV_V_V()
768   assert(LastInst.getDesc().isConditionalBranch() &&  in parseCondBranch()
835     if (J->getDesc().isUnconditionalBranch() ||  in analyzeBranch()
836         J->getDesc().isIndirectBranch()) {  in analyzeBranch()
852   if (I->getDesc().isIndirectBranch())  in analyzeBranch()
860   if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {  in analyzeBranch()
866   if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {  in analyzeBranch()
872   if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&  in analyzeBranch()
873       I->getDesc().isUnconditionalBranch()) {  in analyzeBranch()
891   if (!I->getDesc().isUnconditionalBranch() &&  in removeBranch()
892       !I->getDesc().isConditionalBranch())  in removeBranch()
905   if (!I->getDesc().isConditionalBranch())  in removeBranch()
1001   assert(MI.getDesc().isBranch() && "Unexpected opcode!");  in getBranchDestBlock()
1349       MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))  in getOutliningType()
1422   uint64_t TSFlags = MI.getDesc().TSFlags;  in createMIROperandComment()
1483   const MCInstrDesc &Desc = MI.getDesc();  in findCommutedOpIndices()
1507     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));  in findCommutedOpIndices()
1527     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));  in findCommutedOpIndices()
1771     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&  in convertToThreeAddress()