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Searched refs:getCPU (Results 1 – 25 of 28) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRTargetMachine.cpp32 static StringRef getCPU(StringRef CPU) { in getCPU() function
50 : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options, in AVRTargetMachine()
53 SubTarget(TT, std::string(getCPU(CPU)), std::string(FS), *this) { in AVRTargetMachine()
/llvm-project-15.0.7/llvm/tools/llvm-mca/
H A DPipelinePrinter.cpp48 json::Object SimParameters({{"-mcpu", STI.getCPU()}, in getJSONSimulationParameters()
83 StringRef MCPU = STI.getCPU(); in getJSONTargetInfo()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp434 auto Existing = ArchSubtarget.find(std::string(STI->getCPU())); in getArchSubtarget()
553 if (STI->getCPU().contains("t")) { in addArchSubtarget()
556 STI->getCPU().substr(0, STI->getCPU().size() - 1), FS); in addArchSubtarget()
558 ArchSubtarget[std::string(STI->getCPU())] = in addArchSubtarget()
564 return StringSwitch<unsigned>(STI.getCPU()) in GetELFFlags()
H A DHexagonMCDuplexInfo.cpp636 if (STI.getCPU().equals_insensitive("hexagonv5") || in isOrderedDuplexPair()
637 STI.getCPU().equals_insensitive("hexagonv55") || in isOrderedDuplexPair()
638 STI.getCPU().equals_insensitive("hexagonv60")) { in isOrderedDuplexPair()
H A DHexagonAsmBackend.cpp781 StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU()); in createHexagonAsmBackend()
/llvm-project-15.0.7/clang/lib/Basic/Targets/
H A DMips.h174 const std::string &getCPU() const { return CPU; } in getCPU() function
180 CPU = getCPU(); in initFeatureMap()
H A DMips.cpp62 return llvm::StringSwitch<unsigned>(getCPU()) in getISARev()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp176 AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(STI.getCPU()); in computeWaitCnt()
239 AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(STI.getCPU()); in generateWaitCntInfo()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp548 auto Version = getIsaVersion(STI.getCPU()); in toString()
560 Processor = STI.getCPU().str(); in toString()
725 IsaVersion Version = getIsaVersion(STI->getCPU()); in getSGPRAllocGranule()
738 IsaVersion Version = getIsaVersion(STI->getCPU()); in getTotalNumSGPRs()
748 IsaVersion Version = getIsaVersion(STI->getCPU()); in getAddressableNumSGPRs()
759 IsaVersion Version = getIsaVersion(STI->getCPU()); in getMinNumSGPRs()
778 IsaVersion Version = getIsaVersion(STI->getCPU()); in getMaxNumSGPRs()
796 IsaVersion Version = getIsaVersion(STI->getCPU()); in getNumExtraSGPRs()
909 IsaVersion Version = getIsaVersion(STI->getCPU()); in initDefaultAMDKernelCodeT()
945 IsaVersion Version = getIsaVersion(STI->getCPU()); in getDefaultAmdhsaKernelDescriptor()
/llvm-project-15.0.7/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp173 if (DC->getCPU().empty()) in getItineraryLatency()
178 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU()); in getItineraryLatency()
H A DDisassembler.h118 StringRef getCPU() const { return CPU; } in getCPU() function
/llvm-project-15.0.7/llvm/include/llvm/ExecutionEngine/Orc/
H A DJITTargetMachineBuilder.h83 const std::string &getCPU() const { return CPU; } in getCPU() function
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUTargetStreamer.cpp324 IsaVersion IVersion = getIsaVersion(STI.getCPU()); in EmitAmdhsaKernelDescriptor()
565 return getElfMach(STI.getCPU()); in getEFlagsR600()
626 EFlagsV3 |= getElfMach(STI.getCPU()); in getEFlagsV3()
642 EFlagsV4 |= getElfMach(STI.getCPU()); in getEFlagsV4()
H A DAMDGPUInstPrinter.cpp1482 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); in printWaitFlag()
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMTargetStreamer.cpp133 if (STI.getCPU() == "xscale") in getArchForCPU()
180 const StringRef CPUString = STI.getCPU(); in emitTargetAttributes()
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp603 STI.getCPU(), Options); in createMipsAsmBackend()
604 return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), in createMipsAsmBackend()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h109 StringRef getCPU() const { return CPU; } in getCPU() function
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUMCInstLower.cpp249 if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) && in emitInstruction()
H A DAMDGPUAsmPrinter.cpp151 IsaVersion Version = getIsaVersion(getGlobalSTI()->getCPU()); in initTargetStreamer()
903 if (getIsaVersion(getGlobalSTI()->getCPU()).Major >= 10) { in getSIProgramInfo()
H A DSIMemoryLegalizer.cpp826 IV = getIsaVersion(ST.getCPU()); in SICacheControl()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp222 std::string Subtarget = std::string(SchedModel.getSubtargetInfo()->getCPU()); in shouldReplaceInst()
293 std::string(SchedModel.getSubtargetInfo()->getCPU()); in shouldExitEarly()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYELFStreamer.cpp180 StringRef CPU = STI.getCPU(); in emitTargetAttributes()
/llvm-project-15.0.7/llvm/bindings/ocaml/target/
H A Dllvm_target.mli193 [llvm::TargetMachine::getCPU]. *)
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1367 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in AMDGPUAsmParser()
2858 if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6) in updateGprCountSymbols()
4838 IsaVersion Version = getIsaVersion(getSTI().getCPU()); in calculateGPRBlocks()
4886 IsaVersion IVersion = getIsaVersion(getSTI().getCPU()); in ParseDirectiveAMDHSAKernel()
5257 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in ParseDirectiveHSACodeObjectISA()
6435 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseCnt()
6471 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseSWaitCntOps()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp1395 (Subtarget->getCPU().empty() || Subtarget->getCPU() == "pentium3")) { in LowerPATCHABLE_OP()

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