1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AMDGPU specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AMDGPUTargetStreamer.h"
14 #include "AMDGPUPTNote.h"
15 #include "AMDKernelCodeT.h"
16 #include "Utils/AMDGPUBaseInfo.h"
17 #include "Utils/AMDKernelCodeTUtils.h"
18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h"
19 #include "llvm/BinaryFormat/ELF.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/AMDGPUMetadata.h"
26 #include "llvm/Support/AMDHSAKernelDescriptor.h"
27 #include "llvm/Support/Casting.h"
28 #include "llvm/Support/FormattedStream.h"
29 #include "llvm/Support/TargetParser.h"
30
31 using namespace llvm;
32 using namespace llvm::AMDGPU;
33
34 //===----------------------------------------------------------------------===//
35 // AMDGPUTargetStreamer
36 //===----------------------------------------------------------------------===//
37
convertIsaVersionV2(uint32_t & Major,uint32_t & Minor,uint32_t & Stepping,bool Sramecc,bool Xnack)38 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor,
39 uint32_t &Stepping, bool Sramecc, bool Xnack) {
40 if (Major == 9 && Minor == 0) {
41 switch (Stepping) {
42 case 0:
43 case 2:
44 case 4:
45 case 6:
46 if (Xnack)
47 Stepping++;
48 }
49 }
50 }
51
EmitHSAMetadataV2(StringRef HSAMetadataString)52 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) {
53 HSAMD::Metadata HSAMetadata;
54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
55 return false;
56 return EmitHSAMetadata(HSAMetadata);
57 }
58
EmitHSAMetadataV3(StringRef HSAMetadataString)59 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) {
60 msgpack::Document HSAMetadataDoc;
61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
62 return false;
63 return EmitHSAMetadata(HSAMetadataDoc, false);
64 }
65
getArchNameFromElfMach(unsigned ElfMach)66 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) {
67 AMDGPU::GPUKind AK;
68
69 switch (ElfMach) {
70 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type");
71 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
72 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
73 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
74 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
75 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
76 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
77 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
78 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
79 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break;
80 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break;
81 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break;
82 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
83 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
84 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break;
85 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break;
86 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break;
88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break;
89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break;
90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break;
91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break;
92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break;
93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break;
94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break;
95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break;
96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break;
97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break;
98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break;
99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break;
100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break;
101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break;
102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break;
103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break;
104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break;
105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break;
106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break;
107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break;
108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break;
109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940: AK = GK_GFX940; break;
110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break;
111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break;
112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break;
113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break;
114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break;
115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break;
116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break;
117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break;
118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break;
119 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break;
120 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break;
121 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: AK = GK_GFX1100; break;
122 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: AK = GK_GFX1101; break;
123 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: AK = GK_GFX1102; break;
124 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: AK = GK_GFX1103; break;
125 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
126 }
127
128 StringRef GPUName = getArchNameAMDGCN(AK);
129 if (GPUName != "")
130 return GPUName;
131 return getArchNameR600(AK);
132 }
133
getElfMach(StringRef GPU)134 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
135 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);
136 if (AK == AMDGPU::GPUKind::GK_NONE)
137 AK = parseArchR600(GPU);
138
139 switch (AK) {
140 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600;
141 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630;
142 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880;
143 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670;
144 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710;
145 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730;
146 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770;
147 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR;
148 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS;
149 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER;
150 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD;
151 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO;
152 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS;
153 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS;
154 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN;
155 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS;
156 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600;
157 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601;
158 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602;
159 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700;
160 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701;
161 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702;
162 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703;
163 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704;
164 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705;
165 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801;
166 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802;
167 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803;
168 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805;
169 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810;
170 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900;
171 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902;
172 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;
173 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;
174 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908;
175 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909;
176 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A;
177 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C;
178 case GK_GFX940: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX940;
179 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010;
180 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011;
181 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012;
182 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013;
183 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030;
184 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031;
185 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032;
186 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033;
187 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034;
188 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035;
189 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036;
190 case GK_GFX1100: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100;
191 case GK_GFX1101: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101;
192 case GK_GFX1102: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102;
193 case GK_GFX1103: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103;
194 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
195 }
196
197 llvm_unreachable("unknown GPU");
198 }
199
200 //===----------------------------------------------------------------------===//
201 // AMDGPUTargetAsmStreamer
202 //===----------------------------------------------------------------------===//
203
AMDGPUTargetAsmStreamer(MCStreamer & S,formatted_raw_ostream & OS)204 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S,
205 formatted_raw_ostream &OS)
206 : AMDGPUTargetStreamer(S), OS(OS) { }
207
208 // A hook for emitting stuff at the end.
209 // We use it for emitting the accumulated PAL metadata as directives.
210 // The PAL metadata is reset after it is emitted.
finish()211 void AMDGPUTargetAsmStreamer::finish() {
212 std::string S;
213 getPALMetadata()->toString(S);
214 OS << S;
215
216 // Reset the pal metadata so its data will not affect a compilation that
217 // reuses this object.
218 getPALMetadata()->reset();
219 }
220
EmitDirectiveAMDGCNTarget()221 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() {
222 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
223 }
224
EmitDirectiveHSACodeObjectVersion(uint32_t Major,uint32_t Minor)225 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(
226 uint32_t Major, uint32_t Minor) {
227 OS << "\t.hsa_code_object_version " <<
228 Twine(Major) << "," << Twine(Minor) << '\n';
229 }
230
231 void
EmitDirectiveHSACodeObjectISAV2(uint32_t Major,uint32_t Minor,uint32_t Stepping,StringRef VendorName,StringRef ArchName)232 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major,
233 uint32_t Minor,
234 uint32_t Stepping,
235 StringRef VendorName,
236 StringRef ArchName) {
237 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
238 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << ","
239 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
240 }
241
242 void
EmitAMDKernelCodeT(const amd_kernel_code_t & Header)243 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
244 OS << "\t.amd_kernel_code_t\n";
245 dumpAmdKernelCode(&Header, OS, "\t\t");
246 OS << "\t.end_amd_kernel_code_t\n";
247 }
248
EmitAMDGPUSymbolType(StringRef SymbolName,unsigned Type)249 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
250 unsigned Type) {
251 switch (Type) {
252 default: llvm_unreachable("Invalid AMDGPU symbol type");
253 case ELF::STT_AMDGPU_HSA_KERNEL:
254 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
255 break;
256 }
257 }
258
emitAMDGPULDS(MCSymbol * Symbol,unsigned Size,Align Alignment)259 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
260 Align Alignment) {
261 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
262 << Alignment.value() << '\n';
263 }
264
EmitISAVersion()265 bool AMDGPUTargetAsmStreamer::EmitISAVersion() {
266 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n";
267 return true;
268 }
269
EmitHSAMetadata(const AMDGPU::HSAMD::Metadata & HSAMetadata)270 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
271 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
272 std::string HSAMetadataString;
273 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
274 return false;
275
276 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n';
277 OS << HSAMetadataString << '\n';
278 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n';
279 return true;
280 }
281
EmitHSAMetadata(msgpack::Document & HSAMetadataDoc,bool Strict)282 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
283 msgpack::Document &HSAMetadataDoc, bool Strict) {
284 HSAMD::V3::MetadataVerifier Verifier(Strict);
285 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
286 return false;
287
288 std::string HSAMetadataString;
289 raw_string_ostream StrOS(HSAMetadataString);
290 HSAMetadataDoc.toYAML(StrOS);
291
292 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
293 OS << StrOS.str() << '\n';
294 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
295 return true;
296 }
297
EmitCodeEnd(const MCSubtargetInfo & STI)298 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
299 const uint32_t Encoded_s_code_end = 0xbf9f0000;
300 const uint32_t Encoded_s_nop = 0xbf800000;
301 uint32_t Encoded_pad = Encoded_s_code_end;
302
303 // Instruction cache line size in bytes.
304 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
305 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
306
307 // Extra padding amount in bytes to support prefetch mode 3.
308 unsigned FillSize = 3 * CacheLineSize;
309
310 if (AMDGPU::isGFX90A(STI)) {
311 Encoded_pad = Encoded_s_nop;
312 FillSize = 16 * CacheLineSize;
313 }
314
315 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
316 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
317 return true;
318 }
319
EmitAmdhsaKernelDescriptor(const MCSubtargetInfo & STI,StringRef KernelName,const amdhsa::kernel_descriptor_t & KD,uint64_t NextVGPR,uint64_t NextSGPR,bool ReserveVCC,bool ReserveFlatScr)320 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
321 const MCSubtargetInfo &STI, StringRef KernelName,
322 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
323 bool ReserveVCC, bool ReserveFlatScr) {
324 IsaVersion IVersion = getIsaVersion(STI.getCPU());
325
326 OS << "\t.amdhsa_kernel " << KernelName << '\n';
327
328 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
329 STREAM << "\t\t" << DIRECTIVE << " " \
330 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
331
332 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
333 << '\n';
334 OS << "\t\t.amdhsa_private_segment_fixed_size "
335 << KD.private_segment_fixed_size << '\n';
336 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n';
337
338 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD,
339 compute_pgm_rsrc2,
340 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT);
341
342 if (!hasArchitectedFlatScratch(STI))
343 PRINT_FIELD(
344 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
345 kernel_code_properties,
346 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
347 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
348 kernel_code_properties,
349 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
350 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
351 kernel_code_properties,
352 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
353 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
354 kernel_code_properties,
355 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
356 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
357 kernel_code_properties,
358 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
359 if (!hasArchitectedFlatScratch(STI))
360 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
361 kernel_code_properties,
362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
363 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
364 kernel_code_properties,
365 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
366 if (IVersion.Major >= 10)
367 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD,
368 kernel_code_properties,
369 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
370 PRINT_FIELD(OS, ".amdhsa_uses_dynamic_stack", KD, kernel_code_properties,
371 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
372 PRINT_FIELD(OS,
373 (hasArchitectedFlatScratch(STI)
374 ? ".amdhsa_enable_private_segment"
375 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"),
376 KD, compute_pgm_rsrc2,
377 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
378 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
379 compute_pgm_rsrc2,
380 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
381 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
382 compute_pgm_rsrc2,
383 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
384 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
385 compute_pgm_rsrc2,
386 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
387 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
388 compute_pgm_rsrc2,
389 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
390 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
391 compute_pgm_rsrc2,
392 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
393
394 // These directives are required.
395 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
396 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
397
398 if (AMDGPU::isGFX90A(STI))
399 OS << "\t\t.amdhsa_accum_offset " <<
400 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3,
401 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
402 << '\n';
403
404 if (!ReserveVCC)
405 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
406 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI))
407 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
408
409 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) {
410 switch (*HsaAbiVer) {
411 default:
412 break;
413 case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
414 break;
415 case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
416 case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
417 case ELF::ELFABIVERSION_AMDGPU_HSA_V5:
418 if (getTargetID()->isXnackSupported())
419 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
420 break;
421 }
422 }
423
424 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
425 compute_pgm_rsrc1,
426 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
427 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
428 compute_pgm_rsrc1,
429 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
430 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
431 compute_pgm_rsrc1,
432 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
433 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
434 compute_pgm_rsrc1,
435 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
436 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
437 compute_pgm_rsrc1,
438 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
439 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
440 compute_pgm_rsrc1,
441 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
442 if (IVersion.Major >= 9)
443 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
444 compute_pgm_rsrc1,
445 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
446 if (AMDGPU::isGFX90A(STI))
447 PRINT_FIELD(OS, ".amdhsa_tg_split", KD,
448 compute_pgm_rsrc3,
449 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
450 if (IVersion.Major >= 10) {
451 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD,
452 compute_pgm_rsrc1,
453 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE);
454 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD,
455 compute_pgm_rsrc1,
456 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED);
457 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD,
458 compute_pgm_rsrc1,
459 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS);
460 PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3,
461 amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
462 }
463 PRINT_FIELD(
464 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
465 compute_pgm_rsrc2,
466 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
467 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
468 compute_pgm_rsrc2,
469 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
470 PRINT_FIELD(
471 OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
472 compute_pgm_rsrc2,
473 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
474 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
475 compute_pgm_rsrc2,
476 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
477 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
478 compute_pgm_rsrc2,
479 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
480 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
481 compute_pgm_rsrc2,
482 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
483 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
484 compute_pgm_rsrc2,
485 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
486 #undef PRINT_FIELD
487
488 OS << "\t.end_amdhsa_kernel\n";
489 }
490
491 //===----------------------------------------------------------------------===//
492 // AMDGPUTargetELFStreamer
493 //===----------------------------------------------------------------------===//
494
AMDGPUTargetELFStreamer(MCStreamer & S,const MCSubtargetInfo & STI)495 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S,
496 const MCSubtargetInfo &STI)
497 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {}
498
getStreamer()499 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
500 return static_cast<MCELFStreamer &>(Streamer);
501 }
502
503 // A hook for emitting stuff at the end.
504 // We use it for emitting the accumulated PAL metadata as a .note record.
505 // The PAL metadata is reset after it is emitted.
finish()506 void AMDGPUTargetELFStreamer::finish() {
507 MCAssembler &MCA = getStreamer().getAssembler();
508 MCA.setELFHeaderEFlags(getEFlags());
509
510 std::string Blob;
511 const char *Vendor = getPALMetadata()->getVendor();
512 unsigned Type = getPALMetadata()->getType();
513 getPALMetadata()->toBlob(Type, Blob);
514 if (Blob.empty())
515 return;
516 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
517 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
518
519 // Reset the pal metadata so its data will not affect a compilation that
520 // reuses this object.
521 getPALMetadata()->reset();
522 }
523
EmitNote(StringRef Name,const MCExpr * DescSZ,unsigned NoteType,function_ref<void (MCELFStreamer &)> EmitDesc)524 void AMDGPUTargetELFStreamer::EmitNote(
525 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
526 function_ref<void(MCELFStreamer &)> EmitDesc) {
527 auto &S = getStreamer();
528 auto &Context = S.getContext();
529
530 auto NameSZ = Name.size() + 1;
531
532 unsigned NoteFlags = 0;
533 // TODO Apparently, this is currently needed for OpenCL as mentioned in
534 // https://reviews.llvm.org/D74995
535 if (STI.getTargetTriple().getOS() == Triple::AMDHSA)
536 NoteFlags = ELF::SHF_ALLOC;
537
538 S.pushSection();
539 S.switchSection(
540 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
541 S.emitInt32(NameSZ); // namesz
542 S.emitValue(DescSZ, 4); // descz
543 S.emitInt32(NoteType); // type
544 S.emitBytes(Name); // name
545 S.emitValueToAlignment(4, 0, 1, 0); // padding 0
546 EmitDesc(S); // desc
547 S.emitValueToAlignment(4, 0, 1, 0); // padding 0
548 S.popSection();
549 }
550
getEFlags()551 unsigned AMDGPUTargetELFStreamer::getEFlags() {
552 switch (STI.getTargetTriple().getArch()) {
553 default:
554 llvm_unreachable("Unsupported Arch");
555 case Triple::r600:
556 return getEFlagsR600();
557 case Triple::amdgcn:
558 return getEFlagsAMDGCN();
559 }
560 }
561
getEFlagsR600()562 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
563 assert(STI.getTargetTriple().getArch() == Triple::r600);
564
565 return getElfMach(STI.getCPU());
566 }
567
getEFlagsAMDGCN()568 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
569 assert(STI.getTargetTriple().getArch() == Triple::amdgcn);
570
571 switch (STI.getTargetTriple().getOS()) {
572 default:
573 // TODO: Why are some tests have "mingw" listed as OS?
574 // llvm_unreachable("Unsupported OS");
575 case Triple::UnknownOS:
576 return getEFlagsUnknownOS();
577 case Triple::AMDHSA:
578 return getEFlagsAMDHSA();
579 case Triple::AMDPAL:
580 return getEFlagsAMDPAL();
581 case Triple::Mesa3D:
582 return getEFlagsMesa3D();
583 }
584 }
585
getEFlagsUnknownOS()586 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
587 // TODO: Why are some tests have "mingw" listed as OS?
588 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
589
590 return getEFlagsV3();
591 }
592
getEFlagsAMDHSA()593 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
594 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA);
595
596 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) {
597 switch (*HsaAbiVer) {
598 case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
599 case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
600 return getEFlagsV3();
601 case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
602 case ELF::ELFABIVERSION_AMDGPU_HSA_V5:
603 return getEFlagsV4();
604 }
605 }
606
607 llvm_unreachable("HSA OS ABI Version identification must be defined");
608 }
609
getEFlagsAMDPAL()610 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
611 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL);
612
613 return getEFlagsV3();
614 }
615
getEFlagsMesa3D()616 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
617 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D);
618
619 return getEFlagsV3();
620 }
621
getEFlagsV3()622 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
623 unsigned EFlagsV3 = 0;
624
625 // mach.
626 EFlagsV3 |= getElfMach(STI.getCPU());
627
628 // xnack.
629 if (getTargetID()->isXnackOnOrAny())
630 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3;
631 // sramecc.
632 if (getTargetID()->isSramEccOnOrAny())
633 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3;
634
635 return EFlagsV3;
636 }
637
getEFlagsV4()638 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
639 unsigned EFlagsV4 = 0;
640
641 // mach.
642 EFlagsV4 |= getElfMach(STI.getCPU());
643
644 // xnack.
645 switch (getTargetID()->getXnackSetting()) {
646 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
647 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4;
648 break;
649 case AMDGPU::IsaInfo::TargetIDSetting::Any:
650 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4;
651 break;
652 case AMDGPU::IsaInfo::TargetIDSetting::Off:
653 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4;
654 break;
655 case AMDGPU::IsaInfo::TargetIDSetting::On:
656 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4;
657 break;
658 }
659 // sramecc.
660 switch (getTargetID()->getSramEccSetting()) {
661 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
662 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4;
663 break;
664 case AMDGPU::IsaInfo::TargetIDSetting::Any:
665 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4;
666 break;
667 case AMDGPU::IsaInfo::TargetIDSetting::Off:
668 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4;
669 break;
670 case AMDGPU::IsaInfo::TargetIDSetting::On:
671 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4;
672 break;
673 }
674
675 return EFlagsV4;
676 }
677
EmitDirectiveAMDGCNTarget()678 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {}
679
EmitDirectiveHSACodeObjectVersion(uint32_t Major,uint32_t Minor)680 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(
681 uint32_t Major, uint32_t Minor) {
682
683 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()),
684 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) {
685 OS.emitInt32(Major);
686 OS.emitInt32(Minor);
687 });
688 }
689
690 void
EmitDirectiveHSACodeObjectISAV2(uint32_t Major,uint32_t Minor,uint32_t Stepping,StringRef VendorName,StringRef ArchName)691 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major,
692 uint32_t Minor,
693 uint32_t Stepping,
694 StringRef VendorName,
695 StringRef ArchName) {
696 uint16_t VendorNameSize = VendorName.size() + 1;
697 uint16_t ArchNameSize = ArchName.size() + 1;
698
699 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
700 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
701 VendorNameSize + ArchNameSize;
702
703 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
704 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()),
705 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) {
706 OS.emitInt16(VendorNameSize);
707 OS.emitInt16(ArchNameSize);
708 OS.emitInt32(Major);
709 OS.emitInt32(Minor);
710 OS.emitInt32(Stepping);
711 OS.emitBytes(VendorName);
712 OS.emitInt8(0); // NULL terminate VendorName
713 OS.emitBytes(ArchName);
714 OS.emitInt8(0); // NULL terminate ArchName
715 });
716 }
717
718 void
EmitAMDKernelCodeT(const amd_kernel_code_t & Header)719 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
720
721 MCStreamer &OS = getStreamer();
722 OS.pushSection();
723 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header)));
724 OS.popSection();
725 }
726
EmitAMDGPUSymbolType(StringRef SymbolName,unsigned Type)727 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
728 unsigned Type) {
729 MCSymbolELF *Symbol = cast<MCSymbolELF>(
730 getStreamer().getContext().getOrCreateSymbol(SymbolName));
731 Symbol->setType(Type);
732 }
733
emitAMDGPULDS(MCSymbol * Symbol,unsigned Size,Align Alignment)734 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
735 Align Alignment) {
736 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
737 SymbolELF->setType(ELF::STT_OBJECT);
738
739 if (!SymbolELF->isBindingSet()) {
740 SymbolELF->setBinding(ELF::STB_GLOBAL);
741 SymbolELF->setExternal(true);
742 }
743
744 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) {
745 report_fatal_error("Symbol: " + Symbol->getName() +
746 " redeclared as different type");
747 }
748
749 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
750 SymbolELF->setSize(MCConstantExpr::create(Size, getContext()));
751 }
752
EmitISAVersion()753 bool AMDGPUTargetELFStreamer::EmitISAVersion() {
754 // Create two labels to mark the beginning and end of the desc field
755 // and a MCExpr to calculate the size of the desc field.
756 auto &Context = getContext();
757 auto *DescBegin = Context.createTempSymbol();
758 auto *DescEnd = Context.createTempSymbol();
759 auto *DescSZ = MCBinaryExpr::createSub(
760 MCSymbolRefExpr::create(DescEnd, Context),
761 MCSymbolRefExpr::create(DescBegin, Context), Context);
762
763 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME,
764 [&](MCELFStreamer &OS) {
765 OS.emitLabel(DescBegin);
766 OS.emitBytes(getTargetID()->toString());
767 OS.emitLabel(DescEnd);
768 });
769 return true;
770 }
771
EmitHSAMetadata(msgpack::Document & HSAMetadataDoc,bool Strict)772 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
773 bool Strict) {
774 HSAMD::V3::MetadataVerifier Verifier(Strict);
775 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
776 return false;
777
778 std::string HSAMetadataString;
779 HSAMetadataDoc.writeToBlob(HSAMetadataString);
780
781 // Create two labels to mark the beginning and end of the desc field
782 // and a MCExpr to calculate the size of the desc field.
783 auto &Context = getContext();
784 auto *DescBegin = Context.createTempSymbol();
785 auto *DescEnd = Context.createTempSymbol();
786 auto *DescSZ = MCBinaryExpr::createSub(
787 MCSymbolRefExpr::create(DescEnd, Context),
788 MCSymbolRefExpr::create(DescBegin, Context), Context);
789
790 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA,
791 [&](MCELFStreamer &OS) {
792 OS.emitLabel(DescBegin);
793 OS.emitBytes(HSAMetadataString);
794 OS.emitLabel(DescEnd);
795 });
796 return true;
797 }
798
EmitHSAMetadata(const AMDGPU::HSAMD::Metadata & HSAMetadata)799 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(
800 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
801 std::string HSAMetadataString;
802 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
803 return false;
804
805 // Create two labels to mark the beginning and end of the desc field
806 // and a MCExpr to calculate the size of the desc field.
807 auto &Context = getContext();
808 auto *DescBegin = Context.createTempSymbol();
809 auto *DescEnd = Context.createTempSymbol();
810 auto *DescSZ = MCBinaryExpr::createSub(
811 MCSymbolRefExpr::create(DescEnd, Context),
812 MCSymbolRefExpr::create(DescBegin, Context), Context);
813
814 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA,
815 [&](MCELFStreamer &OS) {
816 OS.emitLabel(DescBegin);
817 OS.emitBytes(HSAMetadataString);
818 OS.emitLabel(DescEnd);
819 });
820 return true;
821 }
822
EmitCodeEnd(const MCSubtargetInfo & STI)823 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
824 const uint32_t Encoded_s_code_end = 0xbf9f0000;
825 const uint32_t Encoded_s_nop = 0xbf800000;
826 uint32_t Encoded_pad = Encoded_s_code_end;
827
828 // Instruction cache line size in bytes.
829 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
830 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
831
832 // Extra padding amount in bytes to support prefetch mode 3.
833 unsigned FillSize = 3 * CacheLineSize;
834
835 if (AMDGPU::isGFX90A(STI)) {
836 Encoded_pad = Encoded_s_nop;
837 FillSize = 16 * CacheLineSize;
838 }
839
840 MCStreamer &OS = getStreamer();
841 OS.pushSection();
842 OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4);
843 for (unsigned I = 0; I < FillSize; I += 4)
844 OS.emitInt32(Encoded_pad);
845 OS.popSection();
846 return true;
847 }
848
EmitAmdhsaKernelDescriptor(const MCSubtargetInfo & STI,StringRef KernelName,const amdhsa::kernel_descriptor_t & KernelDescriptor,uint64_t NextVGPR,uint64_t NextSGPR,bool ReserveVCC,bool ReserveFlatScr)849 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
850 const MCSubtargetInfo &STI, StringRef KernelName,
851 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
852 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) {
853 auto &Streamer = getStreamer();
854 auto &Context = Streamer.getContext();
855
856 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
857 Context.getOrCreateSymbol(Twine(KernelName)));
858 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
859 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
860
861 // Copy kernel descriptor symbol's binding, other and visibility from the
862 // kernel code symbol.
863 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
864 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
865 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
866 // Kernel descriptor symbol's type and size are fixed.
867 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
868 KernelDescriptorSymbol->setSize(
869 MCConstantExpr::create(sizeof(KernelDescriptor), Context));
870
871 // The visibility of the kernel code symbol must be protected or less to allow
872 // static relocations from the kernel descriptor to be used.
873 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
874 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
875
876 Streamer.emitLabel(KernelDescriptorSymbol);
877 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size);
878 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size);
879 Streamer.emitInt32(KernelDescriptor.kernarg_size);
880
881 for (uint8_t Res : KernelDescriptor.reserved0)
882 Streamer.emitInt8(Res);
883
884 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
885 // expression being created is:
886 // (start of kernel code) - (start of kernel descriptor)
887 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
888 Streamer.emitValue(MCBinaryExpr::createSub(
889 MCSymbolRefExpr::create(
890 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
891 MCSymbolRefExpr::create(
892 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
893 Context),
894 sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
895 for (uint8_t Res : KernelDescriptor.reserved1)
896 Streamer.emitInt8(Res);
897 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3);
898 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1);
899 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2);
900 Streamer.emitInt16(KernelDescriptor.kernel_code_properties);
901 for (uint8_t Res : KernelDescriptor.reserved2)
902 Streamer.emitInt8(Res);
903 }
904