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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dhalf-fcmp.ll65 ; RV32I-NEXT: flt.h a0, ft1, ft0
72 ; RV64I-NEXT: flt.h a0, ft1, ft0
113 ; RV32I-NEXT: flt.h a0, ft1, ft0
120 ; RV64I-NEXT: flt.h a0, ft1, ft0
163 ; RV32I-NEXT: flt.h a0, ft1, ft0
164 ; RV32I-NEXT: flt.h a1, ft0, ft1
172 ; RV64I-NEXT: flt.h a0, ft1, ft0
173 ; RV64I-NEXT: flt.h a1, ft0, ft1
224 ; RV32I-NEXT: flt.h a0, ft1, ft0
225 ; RV32I-NEXT: flt.h a1, ft0, ft1
[all …]
H A Dhalf-fcmp-strict.ll22 ; CHECK-NEXT: flt.h a0, fa1, fa0
48 ; CHECK-NEXT: flt.h a0, fa0, fa1
76 ; CHECK-NEXT: flt.h a1, fa0, fa1
80 ; CHECK-NEXT: flt.h a2, fa1, fa0
108 ; CHECK-NEXT: flt.h a1, fa0, fa1
112 ; CHECK-NEXT: flt.h a2, fa1, fa0
141 ; CHECK-NEXT: flt.h a1, fa0, fa1
169 ; CHECK-NEXT: flt.h a1, fa1, fa0
219 ; CHECK-NEXT: flt.h a0, fa1, fa0
239 ; CHECK-NEXT: flt.h a0, fa0, fa1
[all …]
H A Dfloat-select-fcmp.ll34 ; CHECK-NEXT: flt.s a0, fa1, fa0
62 ; CHECK-NEXT: flt.s a0, fa0, fa1
90 ; CHECK-NEXT: flt.s a0, fa0, fa1
91 ; CHECK-NEXT: flt.s a1, fa1, fa0
122 ; CHECK-NEXT: flt.s a0, fa0, fa1
123 ; CHECK-NEXT: flt.s a1, fa1, fa0
152 ; CHECK-NEXT: flt.s a0, fa0, fa1
180 ; CHECK-NEXT: flt.s a0, fa1, fa0
H A Ddouble-select-fcmp.ll34 ; CHECK-NEXT: flt.d a0, fa1, fa0
62 ; CHECK-NEXT: flt.d a0, fa0, fa1
90 ; CHECK-NEXT: flt.d a0, fa0, fa1
91 ; CHECK-NEXT: flt.d a1, fa1, fa0
122 ; CHECK-NEXT: flt.d a0, fa0, fa1
123 ; CHECK-NEXT: flt.d a1, fa1, fa0
152 ; CHECK-NEXT: flt.d a0, fa0, fa1
180 ; CHECK-NEXT: flt.d a0, fa1, fa0
H A Dhalf-select-fcmp.ll34 ; CHECK-NEXT: flt.h a0, fa1, fa0
62 ; CHECK-NEXT: flt.h a0, fa0, fa1
90 ; CHECK-NEXT: flt.h a0, fa0, fa1
91 ; CHECK-NEXT: flt.h a1, fa1, fa0
122 ; CHECK-NEXT: flt.h a0, fa0, fa1
123 ; CHECK-NEXT: flt.h a1, fa1, fa0
152 ; CHECK-NEXT: flt.h a0, fa0, fa1
180 ; CHECK-NEXT: flt.h a0, fa1, fa0
H A Dflt-rounds.ll7 declare i32 @llvm.flt.rounds()
19 %1 = call i32 @llvm.flt.rounds()
H A Ddouble-br-fcmp.ll109 ; RV32IFD-NEXT: flt.d a0, fa1, fa0
120 ; RV64IFD-NEXT: flt.d a0, fa1, fa0
171 ; RV32IFD-NEXT: flt.d a0, fa0, fa1
182 ; RV64IFD-NEXT: flt.d a0, fa0, fa1
233 ; RV32IFD-NEXT: flt.d a0, fa0, fa1
234 ; RV32IFD-NEXT: flt.d a1, fa1, fa0
246 ; RV64IFD-NEXT: flt.d a0, fa0, fa1
247 ; RV64IFD-NEXT: flt.d a1, fa1, fa0
303 ; RV32IFD-NEXT: flt.d a0, fa0, fa1
304 ; RV32IFD-NEXT: flt.d a1, fa1, fa0
[all …]
H A Dhalf-br-fcmp.ll110 ; RV32IZFH-NEXT: flt.h a0, fa1, fa0
121 ; RV64IZFH-NEXT: flt.h a0, fa1, fa0
172 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
183 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
234 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
235 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0
247 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
248 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0
304 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
305 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0
[all …]
H A Dfloat-br-fcmp.ll110 ; RV32IF-NEXT: flt.s a0, fa1, fa0
121 ; RV64IF-NEXT: flt.s a0, fa1, fa0
172 ; RV32IF-NEXT: flt.s a0, fa0, fa1
183 ; RV64IF-NEXT: flt.s a0, fa0, fa1
234 ; RV32IF-NEXT: flt.s a0, fa0, fa1
235 ; RV32IF-NEXT: flt.s a1, fa1, fa0
247 ; RV64IF-NEXT: flt.s a0, fa0, fa1
248 ; RV64IF-NEXT: flt.s a1, fa1, fa0
304 ; RV32IF-NEXT: flt.s a0, fa0, fa1
305 ; RV32IF-NEXT: flt.s a1, fa1, fa0
[all …]
H A Ddouble-previous-failure.ll30 ; RV32IFD-NEXT: flt.d a0, ft0, ft1
32 ; RV32IFD-NEXT: flt.d a1, ft2, ft0
H A Dfloat-fcmp-strict.ll48 ; CHECKIF-NEXT: flt.s a0, fa1, fa0
116 ; CHECKIF-NEXT: flt.s a0, fa0, fa1
184 ; CHECKIF-NEXT: flt.s a1, fa0, fa1
188 ; CHECKIF-NEXT: flt.s a2, fa1, fa0
282 ; CHECKIF-NEXT: flt.s a1, fa0, fa1
286 ; CHECKIF-NEXT: flt.s a2, fa1, fa0
381 ; CHECKIF-NEXT: flt.s a1, fa0, fa1
451 ; CHECKIF-NEXT: flt.s a1, fa1, fa0
581 ; CHECKIF-NEXT: flt.s a0, fa1, fa0
643 ; CHECKIF-NEXT: flt.s a0, fa0, fa1
[all …]
H A Dfpenv.ll25 %rm = call i32 @llvm.flt.rounds()
125 declare i32 @llvm.flt.rounds()
H A Ddouble-fcmp.ll64 ; CHECKIFD-NEXT: flt.d a0, fa1, fa0
126 ; CHECKIFD-NEXT: flt.d a0, fa0, fa1
186 ; CHECKIFD-NEXT: flt.d a0, fa0, fa1
187 ; CHECKIFD-NEXT: flt.d a1, fa1, fa0
284 ; CHECKIFD-NEXT: flt.d a0, fa0, fa1
285 ; CHECKIFD-NEXT: flt.d a1, fa1, fa0
382 ; CHECKIFD-NEXT: flt.d a0, fa0, fa1
446 ; CHECKIFD-NEXT: flt.d a0, fa1, fa0
/llvm-project-15.0.7/llvm/test/ExecutionEngine/
H A Dfrem.ll8 @flt = internal global float 12.0e+0
15 %flt = load float, float* @flt
16 %float2 = frem float %flt, 5.0
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfcvt-fixed.ll12 %fix = fmul float %flt, 128.0
32 %fix = fmul float %flt, 128.0
102 %fix = fmul half %flt, 128.0
122 %fix = fmul half %flt, 32768.0
142 %fix = fmul half %flt, 128.0
162 %fix = fmul half %flt, 32768.0
174 %fix = fmul float %flt, 128.0
194 %fix = fmul float %flt, 128.0
264 %fix = fmul half %flt, 128.0
284 %fix = fmul half %flt, 32768.0
[all …]
H A Dsitofp-fixed-legal.ll25 %flt = sitofp <16 x i32> %in to <16 x double>
26 …%res = fdiv <16 x double> %flt, <double 64.0, double 64.0, double 64.0, double 64.0, double 64.0, …
39 %flt = sitofp <4 x i64> %in to <4 x double>
40 %res = fdiv <4 x double> %flt, <double 64.0, double 64.0, double 64.0, double 64.0>
H A Darm64-fpcr.ll19 %1 = tail call i32 @llvm.flt.rounds()
23 declare i32 @llvm.flt.rounds() #0
/llvm-project-15.0.7/llvm/test/CodeGen/MSP430/
H A Dflt_rounds.ll5 %0 = call i32 @llvm.flt.rounds()
10 declare i32 @llvm.flt.rounds() nounwind
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Ddepgraph.ll62 ; GRAPH-NEXT: [AAPotentialValues] for CtxI <<null inst>> at position {flt: [@-1]} with state set-st…
68 ; GRAPH-NEXT: [AAIsDead] for CtxI ' ret i32* %.0' at position {flt: [@-1]} with state assumed-live
72 ; GRAPH-NEXT: [AAIsDead] for CtxI ' %6 = call i32* @checkAndAdvance(i32* %5)' at position {flt: [@…
105 ; GRAPH-NEXT: [AAIsDead] for CtxI ' %2 = load i32, i32* %0, align 4' at position {flt: [@-1]} with…
107 ; GRAPH-NEXT: [AAIsDead] for CtxI ' %3 = icmp eq i32 %2, 0' at position {flt: [@-1]} with state as…
109 ; GRAPH-NEXT: [AAIsDead] for CtxI ' br i1 %3, label %4, label %7' at position {flt: [@-1]} with st…
137 ; GRAPH-NEXT: [AAPotentialValues] for CtxI <<null inst>> at position {flt: [@-1]} with state set-st…
153 ; GRAPH-NEXT: [AAIsDead] for CtxI ' br label %8' at position {flt: [@-1]} with state assumed-live
216 … for CtxI ' %5 = getelementptr inbounds i32, i32* %0, i64 4' at position {flt: [@-1]} with state …
241 ; GRAPH-NEXT: [AAIsDead] for CtxI ' br label %8' at position {flt: [@-1]} with state assumed-live
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2012-03-05-FPSCR-bug.ll19 %5 = call i32 @llvm.flt.rounds()
36 declare i32 @llvm.flt.rounds() nounwind
H A Dfpscr-intrinsics.ll10 %0 = call i32 @llvm.flt.rounds()
44 declare i32 @llvm.flt.rounds()
H A Dno-fpscr-liveness.ll25 %tmp2 = tail call i32 @llvm.flt.rounds()
50 declare i32 @llvm.flt.rounds()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dflt-rounds.ll6 declare i32 @llvm.flt.rounds()
34 %1 = call i32 @llvm.flt.rounds()
175 %0 = tail call i32 @llvm.flt.rounds()
179 %1 = tail call i32 @llvm.flt.rounds()
184 %2 = tail call i32 @llvm.flt.rounds()
189 %3 = tail call i32 @llvm.flt.rounds()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfrounds.ll69 %tmp1 = call i32 @llvm.flt.rounds( ) ; <i32> [#uses=1]
80 declare i32 @llvm.flt.rounds() nounwind
/llvm-project-15.0.7/mlir/test/Dialect/MemRef/
H A Dinvalid.mlir27 %tag: memref<i32,2>, %flt: f32) {
29 "memref.dma_start"(%src, %idx, %flt, %dst, %idx, %tag, %idx)
55 %tag: memref<i32,2>, %flt: f32) {
57 "memref.dma_start"(%src, %idx, %idx, %dst, %flt, %tag, %idx)
65 %tag: memref<i32,2>, %flt: f32) {
67 "memref.dma_start"(%src, %idx, %idx, %dst, %idx, %flt, %tag)
93 %tag: memref<2xi32,2>, %flt: f32) {
95 "memref.dma_start"(%src, %idx, %idx, %dst, %idx, %idx, %tag, %flt)
114 %tag: memref<i32,2>, %flt: f32) {
116 "memref.dma_start"(%src, %idx, %idx, %dst, %idx, %idx, %tag, %idx, %flt)
[all …]

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