1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-NO16 3; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 4 5; fptoui 6 7define i32 @fcvtzs_f32_i32_7(float %flt) { 8; CHECK-LABEL: fcvtzs_f32_i32_7: 9; CHECK: // %bb.0: 10; CHECK-NEXT: fcvtzs w0, s0, #7 11; CHECK-NEXT: ret 12 %fix = fmul float %flt, 128.0 13 %cvt = fptosi float %fix to i32 14 ret i32 %cvt 15} 16 17define i32 @fcvtzs_f32_i32_32(float %flt) { 18; CHECK-LABEL: fcvtzs_f32_i32_32: 19; CHECK: // %bb.0: 20; CHECK-NEXT: fcvtzs w0, s0, #32 21; CHECK-NEXT: ret 22 %fix = fmul float %flt, 4294967296.0 23 %cvt = fptosi float %fix to i32 24 ret i32 %cvt 25} 26 27define i64 @fcvtzs_f32_i64_7(float %flt) { 28; CHECK-LABEL: fcvtzs_f32_i64_7: 29; CHECK: // %bb.0: 30; CHECK-NEXT: fcvtzs x0, s0, #7 31; CHECK-NEXT: ret 32 %fix = fmul float %flt, 128.0 33 %cvt = fptosi float %fix to i64 34 ret i64 %cvt 35} 36 37define i64 @fcvtzs_f32_i64_64(float %flt) { 38; CHECK-LABEL: fcvtzs_f32_i64_64: 39; CHECK: // %bb.0: 40; CHECK-NEXT: fcvtzs x0, s0, #64 41; CHECK-NEXT: ret 42 %fix = fmul float %flt, 18446744073709551616.0 43 %cvt = fptosi float %fix to i64 44 ret i64 %cvt 45} 46 47define i32 @fcvtzs_f64_i32_7(double %dbl) { 48; CHECK-LABEL: fcvtzs_f64_i32_7: 49; CHECK: // %bb.0: 50; CHECK-NEXT: fcvtzs w0, d0, #7 51; CHECK-NEXT: ret 52 %fix = fmul double %dbl, 128.0 53 %cvt = fptosi double %fix to i32 54 ret i32 %cvt 55} 56 57define i32 @fcvtzs_f64_i32_32(double %dbl) { 58; CHECK-LABEL: fcvtzs_f64_i32_32: 59; CHECK: // %bb.0: 60; CHECK-NEXT: fcvtzs w0, d0, #32 61; CHECK-NEXT: ret 62 %fix = fmul double %dbl, 4294967296.0 63 %cvt = fptosi double %fix to i32 64 ret i32 %cvt 65} 66 67define i64 @fcvtzs_f64_i64_7(double %dbl) { 68; CHECK-LABEL: fcvtzs_f64_i64_7: 69; CHECK: // %bb.0: 70; CHECK-NEXT: fcvtzs x0, d0, #7 71; CHECK-NEXT: ret 72 %fix = fmul double %dbl, 128.0 73 %cvt = fptosi double %fix to i64 74 ret i64 %cvt 75} 76 77define i64 @fcvtzs_f64_i64_64(double %dbl) { 78; CHECK-LABEL: fcvtzs_f64_i64_64: 79; CHECK: // %bb.0: 80; CHECK-NEXT: fcvtzs x0, d0, #64 81; CHECK-NEXT: ret 82 %fix = fmul double %dbl, 18446744073709551616.0 83 %cvt = fptosi double %fix to i64 84 ret i64 %cvt 85} 86 87define i32 @fcvtzs_f16_i32_7(half %flt) { 88; CHECK-NO16-LABEL: fcvtzs_f16_i32_7: 89; CHECK-NO16: // %bb.0: 90; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24 91; CHECK-NO16-NEXT: fcvt s0, h0 92; CHECK-NO16-NEXT: fmul s0, s0, s1 93; CHECK-NO16-NEXT: fcvt h0, s0 94; CHECK-NO16-NEXT: fcvt s0, h0 95; CHECK-NO16-NEXT: fcvtzs w0, s0 96; CHECK-NO16-NEXT: ret 97; 98; CHECK-FP16-LABEL: fcvtzs_f16_i32_7: 99; CHECK-FP16: // %bb.0: 100; CHECK-FP16-NEXT: fcvtzs w0, h0, #7 101; CHECK-FP16-NEXT: ret 102 %fix = fmul half %flt, 128.0 103 %cvt = fptosi half %fix to i32 104 ret i32 %cvt 105} 106 107define i32 @fcvtzs_f16_i32_15(half %flt) { 108; CHECK-NO16-LABEL: fcvtzs_f16_i32_15: 109; CHECK-NO16: // %bb.0: 110; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24 111; CHECK-NO16-NEXT: fcvt s0, h0 112; CHECK-NO16-NEXT: fmul s0, s0, s1 113; CHECK-NO16-NEXT: fcvt h0, s0 114; CHECK-NO16-NEXT: fcvt s0, h0 115; CHECK-NO16-NEXT: fcvtzs w0, s0 116; CHECK-NO16-NEXT: ret 117; 118; CHECK-FP16-LABEL: fcvtzs_f16_i32_15: 119; CHECK-FP16: // %bb.0: 120; CHECK-FP16-NEXT: fcvtzs w0, h0, #15 121; CHECK-FP16-NEXT: ret 122 %fix = fmul half %flt, 32768.0 123 %cvt = fptosi half %fix to i32 124 ret i32 %cvt 125} 126 127define i64 @fcvtzs_f16_i64_7(half %flt) { 128; CHECK-NO16-LABEL: fcvtzs_f16_i64_7: 129; CHECK-NO16: // %bb.0: 130; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24 131; CHECK-NO16-NEXT: fcvt s0, h0 132; CHECK-NO16-NEXT: fmul s0, s0, s1 133; CHECK-NO16-NEXT: fcvt h0, s0 134; CHECK-NO16-NEXT: fcvt s0, h0 135; CHECK-NO16-NEXT: fcvtzs x0, s0 136; CHECK-NO16-NEXT: ret 137; 138; CHECK-FP16-LABEL: fcvtzs_f16_i64_7: 139; CHECK-FP16: // %bb.0: 140; CHECK-FP16-NEXT: fcvtzs x0, h0, #7 141; CHECK-FP16-NEXT: ret 142 %fix = fmul half %flt, 128.0 143 %cvt = fptosi half %fix to i64 144 ret i64 %cvt 145} 146 147define i64 @fcvtzs_f16_i64_15(half %flt) { 148; CHECK-NO16-LABEL: fcvtzs_f16_i64_15: 149; CHECK-NO16: // %bb.0: 150; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24 151; CHECK-NO16-NEXT: fcvt s0, h0 152; CHECK-NO16-NEXT: fmul s0, s0, s1 153; CHECK-NO16-NEXT: fcvt h0, s0 154; CHECK-NO16-NEXT: fcvt s0, h0 155; CHECK-NO16-NEXT: fcvtzs x0, s0 156; CHECK-NO16-NEXT: ret 157; 158; CHECK-FP16-LABEL: fcvtzs_f16_i64_15: 159; CHECK-FP16: // %bb.0: 160; CHECK-FP16-NEXT: fcvtzs x0, h0, #15 161; CHECK-FP16-NEXT: ret 162 %fix = fmul half %flt, 32768.0 163 %cvt = fptosi half %fix to i64 164 ret i64 %cvt 165} 166 167; fptoui 168 169define i32 @fcvtzu_f32_i32_7(float %flt) { 170; CHECK-LABEL: fcvtzu_f32_i32_7: 171; CHECK: // %bb.0: 172; CHECK-NEXT: fcvtzu w0, s0, #7 173; CHECK-NEXT: ret 174 %fix = fmul float %flt, 128.0 175 %cvt = fptoui float %fix to i32 176 ret i32 %cvt 177} 178 179define i32 @fcvtzu_f32_i32_32(float %flt) { 180; CHECK-LABEL: fcvtzu_f32_i32_32: 181; CHECK: // %bb.0: 182; CHECK-NEXT: fcvtzu w0, s0, #32 183; CHECK-NEXT: ret 184 %fix = fmul float %flt, 4294967296.0 185 %cvt = fptoui float %fix to i32 186 ret i32 %cvt 187} 188 189define i64 @fcvtzu_f32_i64_7(float %flt) { 190; CHECK-LABEL: fcvtzu_f32_i64_7: 191; CHECK: // %bb.0: 192; CHECK-NEXT: fcvtzu x0, s0, #7 193; CHECK-NEXT: ret 194 %fix = fmul float %flt, 128.0 195 %cvt = fptoui float %fix to i64 196 ret i64 %cvt 197} 198 199define i64 @fcvtzu_f32_i64_64(float %flt) { 200; CHECK-LABEL: fcvtzu_f32_i64_64: 201; CHECK: // %bb.0: 202; CHECK-NEXT: fcvtzu x0, s0, #64 203; CHECK-NEXT: ret 204 %fix = fmul float %flt, 18446744073709551616.0 205 %cvt = fptoui float %fix to i64 206 ret i64 %cvt 207} 208 209define i32 @fcvtzu_f64_i32_7(double %dbl) { 210; CHECK-LABEL: fcvtzu_f64_i32_7: 211; CHECK: // %bb.0: 212; CHECK-NEXT: fcvtzu w0, d0, #7 213; CHECK-NEXT: ret 214 %fix = fmul double %dbl, 128.0 215 %cvt = fptoui double %fix to i32 216 ret i32 %cvt 217} 218 219define i32 @fcvtzu_f64_i32_32(double %dbl) { 220; CHECK-LABEL: fcvtzu_f64_i32_32: 221; CHECK: // %bb.0: 222; CHECK-NEXT: fcvtzu w0, d0, #32 223; CHECK-NEXT: ret 224 %fix = fmul double %dbl, 4294967296.0 225 %cvt = fptoui double %fix to i32 226 ret i32 %cvt 227} 228 229define i64 @fcvtzu_f64_i64_7(double %dbl) { 230; CHECK-LABEL: fcvtzu_f64_i64_7: 231; CHECK: // %bb.0: 232; CHECK-NEXT: fcvtzu x0, d0, #7 233; CHECK-NEXT: ret 234 %fix = fmul double %dbl, 128.0 235 %cvt = fptoui double %fix to i64 236 ret i64 %cvt 237} 238 239define i64 @fcvtzu_f64_i64_64(double %dbl) { 240; CHECK-LABEL: fcvtzu_f64_i64_64: 241; CHECK: // %bb.0: 242; CHECK-NEXT: fcvtzu x0, d0, #64 243; CHECK-NEXT: ret 244 %fix = fmul double %dbl, 18446744073709551616.0 245 %cvt = fptoui double %fix to i64 246 ret i64 %cvt 247} 248 249define i32 @fcvtzu_f16_i32_7(half %flt) { 250; CHECK-NO16-LABEL: fcvtzu_f16_i32_7: 251; CHECK-NO16: // %bb.0: 252; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24 253; CHECK-NO16-NEXT: fcvt s0, h0 254; CHECK-NO16-NEXT: fmul s0, s0, s1 255; CHECK-NO16-NEXT: fcvt h0, s0 256; CHECK-NO16-NEXT: fcvt s0, h0 257; CHECK-NO16-NEXT: fcvtzu w0, s0 258; CHECK-NO16-NEXT: ret 259; 260; CHECK-FP16-LABEL: fcvtzu_f16_i32_7: 261; CHECK-FP16: // %bb.0: 262; CHECK-FP16-NEXT: fcvtzu w0, h0, #7 263; CHECK-FP16-NEXT: ret 264 %fix = fmul half %flt, 128.0 265 %cvt = fptoui half %fix to i32 266 ret i32 %cvt 267} 268 269define i32 @fcvtzu_f16_i32_15(half %flt) { 270; CHECK-NO16-LABEL: fcvtzu_f16_i32_15: 271; CHECK-NO16: // %bb.0: 272; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24 273; CHECK-NO16-NEXT: fcvt s0, h0 274; CHECK-NO16-NEXT: fmul s0, s0, s1 275; CHECK-NO16-NEXT: fcvt h0, s0 276; CHECK-NO16-NEXT: fcvt s0, h0 277; CHECK-NO16-NEXT: fcvtzu w0, s0 278; CHECK-NO16-NEXT: ret 279; 280; CHECK-FP16-LABEL: fcvtzu_f16_i32_15: 281; CHECK-FP16: // %bb.0: 282; CHECK-FP16-NEXT: fcvtzu w0, h0, #15 283; CHECK-FP16-NEXT: ret 284 %fix = fmul half %flt, 32768.0 285 %cvt = fptoui half %fix to i32 286 ret i32 %cvt 287} 288 289define i64 @fcvtzu_f16_i64_7(half %flt) { 290; CHECK-NO16-LABEL: fcvtzu_f16_i64_7: 291; CHECK-NO16: // %bb.0: 292; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24 293; CHECK-NO16-NEXT: fcvt s0, h0 294; CHECK-NO16-NEXT: fmul s0, s0, s1 295; CHECK-NO16-NEXT: fcvt h0, s0 296; CHECK-NO16-NEXT: fcvt s0, h0 297; CHECK-NO16-NEXT: fcvtzu x0, s0 298; CHECK-NO16-NEXT: ret 299; 300; CHECK-FP16-LABEL: fcvtzu_f16_i64_7: 301; CHECK-FP16: // %bb.0: 302; CHECK-FP16-NEXT: fcvtzu x0, h0, #7 303; CHECK-FP16-NEXT: ret 304 %fix = fmul half %flt, 128.0 305 %cvt = fptoui half %fix to i64 306 ret i64 %cvt 307} 308 309define i64 @fcvtzu_f16_i64_15(half %flt) { 310; CHECK-NO16-LABEL: fcvtzu_f16_i64_15: 311; CHECK-NO16: // %bb.0: 312; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24 313; CHECK-NO16-NEXT: fcvt s0, h0 314; CHECK-NO16-NEXT: fmul s0, s0, s1 315; CHECK-NO16-NEXT: fcvt h0, s0 316; CHECK-NO16-NEXT: fcvt s0, h0 317; CHECK-NO16-NEXT: fcvtzu x0, s0 318; CHECK-NO16-NEXT: ret 319; 320; CHECK-FP16-LABEL: fcvtzu_f16_i64_15: 321; CHECK-FP16: // %bb.0: 322; CHECK-FP16-NEXT: fcvtzu x0, h0, #15 323; CHECK-FP16-NEXT: ret 324 %fix = fmul half %flt, 32768.0 325 %cvt = fptoui half %fix to i64 326 ret i64 %cvt 327} 328 329; sitofp 330 331define float @scvtf_f32_i32_7(i32 %int) { 332; CHECK-LABEL: scvtf_f32_i32_7: 333; CHECK: // %bb.0: 334; CHECK-NEXT: scvtf s0, w0, #7 335; CHECK-NEXT: ret 336 %cvt = sitofp i32 %int to float 337 %fix = fdiv float %cvt, 128.0 338 ret float %fix 339} 340 341define float @scvtf_f32_i32_32(i32 %int) { 342; CHECK-LABEL: scvtf_f32_i32_32: 343; CHECK: // %bb.0: 344; CHECK-NEXT: scvtf s0, w0, #32 345; CHECK-NEXT: ret 346 %cvt = sitofp i32 %int to float 347 %fix = fdiv float %cvt, 4294967296.0 348 ret float %fix 349} 350 351define float @scvtf_f32_i64_7(i64 %long) { 352; CHECK-LABEL: scvtf_f32_i64_7: 353; CHECK: // %bb.0: 354; CHECK-NEXT: scvtf s0, x0, #7 355; CHECK-NEXT: ret 356 %cvt = sitofp i64 %long to float 357 %fix = fdiv float %cvt, 128.0 358 ret float %fix 359} 360 361define float @scvtf_f32_i64_64(i64 %long) { 362; CHECK-LABEL: scvtf_f32_i64_64: 363; CHECK: // %bb.0: 364; CHECK-NEXT: scvtf s0, x0, #64 365; CHECK-NEXT: ret 366 %cvt = sitofp i64 %long to float 367 %fix = fdiv float %cvt, 18446744073709551616.0 368 ret float %fix 369} 370 371define double @scvtf_f64_i32_7(i32 %int) { 372; CHECK-LABEL: scvtf_f64_i32_7: 373; CHECK: // %bb.0: 374; CHECK-NEXT: scvtf d0, w0, #7 375; CHECK-NEXT: ret 376 %cvt = sitofp i32 %int to double 377 %fix = fdiv double %cvt, 128.0 378 ret double %fix 379} 380 381define double @scvtf_f64_i32_32(i32 %int) { 382; CHECK-LABEL: scvtf_f64_i32_32: 383; CHECK: // %bb.0: 384; CHECK-NEXT: scvtf d0, w0, #32 385; CHECK-NEXT: ret 386 %cvt = sitofp i32 %int to double 387 %fix = fdiv double %cvt, 4294967296.0 388 ret double %fix 389} 390 391define double @scvtf_f64_i64_7(i64 %long) { 392; CHECK-LABEL: scvtf_f64_i64_7: 393; CHECK: // %bb.0: 394; CHECK-NEXT: scvtf d0, x0, #7 395; CHECK-NEXT: ret 396 %cvt = sitofp i64 %long to double 397 %fix = fdiv double %cvt, 128.0 398 ret double %fix 399} 400 401define double @scvtf_f64_i64_64(i64 %long) { 402; CHECK-LABEL: scvtf_f64_i64_64: 403; CHECK: // %bb.0: 404; CHECK-NEXT: scvtf d0, x0, #64 405; CHECK-NEXT: ret 406 %cvt = sitofp i64 %long to double 407 %fix = fdiv double %cvt, 18446744073709551616.0 408 ret double %fix 409} 410 411define half @scvtf_f16_i32_7(i32 %int) { 412; CHECK-NO16-LABEL: scvtf_f16_i32_7: 413; CHECK-NO16: // %bb.0: 414; CHECK-NO16-NEXT: scvtf s1, w0 415; CHECK-NO16-NEXT: movi v0.2s, #67, lsl #24 416; CHECK-NO16-NEXT: fcvt h1, s1 417; CHECK-NO16-NEXT: fcvt s1, h1 418; CHECK-NO16-NEXT: fdiv s0, s1, s0 419; CHECK-NO16-NEXT: fcvt h0, s0 420; CHECK-NO16-NEXT: ret 421; 422; CHECK-FP16-LABEL: scvtf_f16_i32_7: 423; CHECK-FP16: // %bb.0: 424; CHECK-FP16-NEXT: scvtf h0, w0, #7 425; CHECK-FP16-NEXT: ret 426 %cvt = sitofp i32 %int to half 427 %fix = fdiv half %cvt, 128.0 428 ret half %fix 429} 430 431define half @scvtf_f16_i32_15(i32 %int) { 432; CHECK-NO16-LABEL: scvtf_f16_i32_15: 433; CHECK-NO16: // %bb.0: 434; CHECK-NO16-NEXT: scvtf s1, w0 435; CHECK-NO16-NEXT: movi v0.2s, #71, lsl #24 436; CHECK-NO16-NEXT: fcvt h1, s1 437; CHECK-NO16-NEXT: fcvt s1, h1 438; CHECK-NO16-NEXT: fdiv s0, s1, s0 439; CHECK-NO16-NEXT: fcvt h0, s0 440; CHECK-NO16-NEXT: ret 441; 442; CHECK-FP16-LABEL: scvtf_f16_i32_15: 443; CHECK-FP16: // %bb.0: 444; CHECK-FP16-NEXT: scvtf h0, w0, #15 445; CHECK-FP16-NEXT: ret 446 %cvt = sitofp i32 %int to half 447 %fix = fdiv half %cvt, 32768.0 448 ret half %fix 449} 450 451define half @scvtf_f16_i64_7(i64 %long) { 452; CHECK-NO16-LABEL: scvtf_f16_i64_7: 453; CHECK-NO16: // %bb.0: 454; CHECK-NO16-NEXT: scvtf s1, x0 455; CHECK-NO16-NEXT: movi v0.2s, #67, lsl #24 456; CHECK-NO16-NEXT: fcvt h1, s1 457; CHECK-NO16-NEXT: fcvt s1, h1 458; CHECK-NO16-NEXT: fdiv s0, s1, s0 459; CHECK-NO16-NEXT: fcvt h0, s0 460; CHECK-NO16-NEXT: ret 461; 462; CHECK-FP16-LABEL: scvtf_f16_i64_7: 463; CHECK-FP16: // %bb.0: 464; CHECK-FP16-NEXT: scvtf h0, x0, #7 465; CHECK-FP16-NEXT: ret 466 %cvt = sitofp i64 %long to half 467 %fix = fdiv half %cvt, 128.0 468 ret half %fix 469} 470 471define half @scvtf_f16_i64_15(i64 %long) { 472; CHECK-NO16-LABEL: scvtf_f16_i64_15: 473; CHECK-NO16: // %bb.0: 474; CHECK-NO16-NEXT: scvtf s1, x0 475; CHECK-NO16-NEXT: movi v0.2s, #71, lsl #24 476; CHECK-NO16-NEXT: fcvt h1, s1 477; CHECK-NO16-NEXT: fcvt s1, h1 478; CHECK-NO16-NEXT: fdiv s0, s1, s0 479; CHECK-NO16-NEXT: fcvt h0, s0 480; CHECK-NO16-NEXT: ret 481; 482; CHECK-FP16-LABEL: scvtf_f16_i64_15: 483; CHECK-FP16: // %bb.0: 484; CHECK-FP16-NEXT: scvtf h0, x0, #15 485; CHECK-FP16-NEXT: ret 486 %cvt = sitofp i64 %long to half 487 %fix = fdiv half %cvt, 32768.0 488 ret half %fix 489} 490 491; uitofp 492 493define float @ucvtf_f32_i32_7(i32 %int) { 494; CHECK-LABEL: ucvtf_f32_i32_7: 495; CHECK: // %bb.0: 496; CHECK-NEXT: ucvtf s0, w0, #7 497; CHECK-NEXT: ret 498 %cvt = uitofp i32 %int to float 499 %fix = fdiv float %cvt, 128.0 500 ret float %fix 501} 502 503define float @ucvtf_f32_i32_32(i32 %int) { 504; CHECK-LABEL: ucvtf_f32_i32_32: 505; CHECK: // %bb.0: 506; CHECK-NEXT: ucvtf s0, w0, #32 507; CHECK-NEXT: ret 508 %cvt = uitofp i32 %int to float 509 %fix = fdiv float %cvt, 4294967296.0 510 ret float %fix 511} 512 513define float @ucvtf_f32_i64_7(i64 %long) { 514; CHECK-LABEL: ucvtf_f32_i64_7: 515; CHECK: // %bb.0: 516; CHECK-NEXT: ucvtf s0, x0, #7 517; CHECK-NEXT: ret 518 %cvt = uitofp i64 %long to float 519 %fix = fdiv float %cvt, 128.0 520 ret float %fix 521} 522 523define float @ucvtf_f32_i64_64(i64 %long) { 524; CHECK-LABEL: ucvtf_f32_i64_64: 525; CHECK: // %bb.0: 526; CHECK-NEXT: ucvtf s0, x0, #64 527; CHECK-NEXT: ret 528 %cvt = uitofp i64 %long to float 529 %fix = fdiv float %cvt, 18446744073709551616.0 530 ret float %fix 531} 532 533define double @ucvtf_f64_i32_7(i32 %int) { 534; CHECK-LABEL: ucvtf_f64_i32_7: 535; CHECK: // %bb.0: 536; CHECK-NEXT: ucvtf d0, w0, #7 537; CHECK-NEXT: ret 538 %cvt = uitofp i32 %int to double 539 %fix = fdiv double %cvt, 128.0 540 ret double %fix 541} 542 543define double @ucvtf_f64_i32_32(i32 %int) { 544; CHECK-LABEL: ucvtf_f64_i32_32: 545; CHECK: // %bb.0: 546; CHECK-NEXT: ucvtf d0, w0, #32 547; CHECK-NEXT: ret 548 %cvt = uitofp i32 %int to double 549 %fix = fdiv double %cvt, 4294967296.0 550 ret double %fix 551} 552 553define double @ucvtf_f64_i64_7(i64 %long) { 554; CHECK-LABEL: ucvtf_f64_i64_7: 555; CHECK: // %bb.0: 556; CHECK-NEXT: ucvtf d0, x0, #7 557; CHECK-NEXT: ret 558 %cvt = uitofp i64 %long to double 559 %fix = fdiv double %cvt, 128.0 560 ret double %fix 561} 562 563define double @ucvtf_f64_i64_64(i64 %long) { 564; CHECK-LABEL: ucvtf_f64_i64_64: 565; CHECK: // %bb.0: 566; CHECK-NEXT: ucvtf d0, x0, #64 567; CHECK-NEXT: ret 568 %cvt = uitofp i64 %long to double 569 %fix = fdiv double %cvt, 18446744073709551616.0 570 ret double %fix 571} 572 573define half @ucvtf_f16_i32_7(i32 %int) { 574; CHECK-NO16-LABEL: ucvtf_f16_i32_7: 575; CHECK-NO16: // %bb.0: 576; CHECK-NO16-NEXT: ucvtf s1, w0 577; CHECK-NO16-NEXT: movi v0.2s, #67, lsl #24 578; CHECK-NO16-NEXT: fcvt h1, s1 579; CHECK-NO16-NEXT: fcvt s1, h1 580; CHECK-NO16-NEXT: fdiv s0, s1, s0 581; CHECK-NO16-NEXT: fcvt h0, s0 582; CHECK-NO16-NEXT: ret 583; 584; CHECK-FP16-LABEL: ucvtf_f16_i32_7: 585; CHECK-FP16: // %bb.0: 586; CHECK-FP16-NEXT: ucvtf h0, w0, #7 587; CHECK-FP16-NEXT: ret 588 %cvt = uitofp i32 %int to half 589 %fix = fdiv half %cvt, 128.0 590 ret half %fix 591} 592 593define half @ucvtf_f16_i32_15(i32 %int) { 594; CHECK-NO16-LABEL: ucvtf_f16_i32_15: 595; CHECK-NO16: // %bb.0: 596; CHECK-NO16-NEXT: ucvtf s1, w0 597; CHECK-NO16-NEXT: movi v0.2s, #71, lsl #24 598; CHECK-NO16-NEXT: fcvt h1, s1 599; CHECK-NO16-NEXT: fcvt s1, h1 600; CHECK-NO16-NEXT: fdiv s0, s1, s0 601; CHECK-NO16-NEXT: fcvt h0, s0 602; CHECK-NO16-NEXT: ret 603; 604; CHECK-FP16-LABEL: ucvtf_f16_i32_15: 605; CHECK-FP16: // %bb.0: 606; CHECK-FP16-NEXT: ucvtf h0, w0, #15 607; CHECK-FP16-NEXT: ret 608 %cvt = uitofp i32 %int to half 609 %fix = fdiv half %cvt, 32768.0 610 ret half %fix 611} 612 613define half @ucvtf_f16_i64_7(i64 %long) { 614; CHECK-NO16-LABEL: ucvtf_f16_i64_7: 615; CHECK-NO16: // %bb.0: 616; CHECK-NO16-NEXT: ucvtf s1, x0 617; CHECK-NO16-NEXT: movi v0.2s, #67, lsl #24 618; CHECK-NO16-NEXT: fcvt h1, s1 619; CHECK-NO16-NEXT: fcvt s1, h1 620; CHECK-NO16-NEXT: fdiv s0, s1, s0 621; CHECK-NO16-NEXT: fcvt h0, s0 622; CHECK-NO16-NEXT: ret 623; 624; CHECK-FP16-LABEL: ucvtf_f16_i64_7: 625; CHECK-FP16: // %bb.0: 626; CHECK-FP16-NEXT: ucvtf h0, x0, #7 627; CHECK-FP16-NEXT: ret 628 %cvt = uitofp i64 %long to half 629 %fix = fdiv half %cvt, 128.0 630 ret half %fix 631} 632 633define half @ucvtf_f16_i64_15(i64 %long) { 634; CHECK-NO16-LABEL: ucvtf_f16_i64_15: 635; CHECK-NO16: // %bb.0: 636; CHECK-NO16-NEXT: ucvtf s1, x0 637; CHECK-NO16-NEXT: movi v0.2s, #71, lsl #24 638; CHECK-NO16-NEXT: fcvt h1, s1 639; CHECK-NO16-NEXT: fcvt s1, h1 640; CHECK-NO16-NEXT: fdiv s0, s1, s0 641; CHECK-NO16-NEXT: fcvt h0, s0 642; CHECK-NO16-NEXT: ret 643; 644; CHECK-FP16-LABEL: ucvtf_f16_i64_15: 645; CHECK-FP16: // %bb.0: 646; CHECK-FP16-NEXT: ucvtf h0, x0, #15 647; CHECK-FP16-NEXT: ret 648 %cvt = uitofp i64 %long to half 649 %fix = fdiv half %cvt, 32768.0 650 ret half %fix 651} 652 653 654; fptoui.sat 655 656declare i32 @llvm.fptosi.sat.i32.f32(float) 657declare i64 @llvm.fptosi.sat.i64.f32(float) 658declare i32 @llvm.fptosi.sat.i32.f64(double) 659declare i64 @llvm.fptosi.sat.i64.f64(double) 660declare i32 @llvm.fptosi.sat.i32.f16(half) 661declare i64 @llvm.fptosi.sat.i64.f16(half) 662 663define i32 @fcvtzs_sat_f32_i32_7(float %flt) { 664; CHECK-LABEL: fcvtzs_sat_f32_i32_7: 665; CHECK: // %bb.0: 666; CHECK-NEXT: fcvtzs w0, s0, #7 667; CHECK-NEXT: ret 668 %fix = fmul float %flt, 128.0 669 %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix) 670 ret i32 %cvt 671} 672 673define i32 @fcvtzs_sat_f32_i32_32(float %flt) { 674; CHECK-LABEL: fcvtzs_sat_f32_i32_32: 675; CHECK: // %bb.0: 676; CHECK-NEXT: fcvtzs w0, s0, #32 677; CHECK-NEXT: ret 678 %fix = fmul float %flt, 4294967296.0 679 %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix) 680 ret i32 %cvt 681} 682 683define i64 @fcvtzs_sat_f32_i64_64(float %flt) { 684; CHECK-LABEL: fcvtzs_sat_f32_i64_64: 685; CHECK: // %bb.0: 686; CHECK-NEXT: fcvtzs x0, s0, #64 687; CHECK-NEXT: ret 688 %fix = fmul float %flt, 18446744073709551616.0 689 %cvt = call i64 @llvm.fptosi.sat.i64.f32(float %fix) 690 ret i64 %cvt 691} 692 693define i32 @fcvtzs_sat_f64_i32_7(double %dbl) { 694; CHECK-LABEL: fcvtzs_sat_f64_i32_7: 695; CHECK: // %bb.0: 696; CHECK-NEXT: fcvtzs w0, d0, #7 697; CHECK-NEXT: ret 698 %fix = fmul double %dbl, 128.0 699 %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix) 700 ret i32 %cvt 701} 702 703define i32 @fcvtzs_sat_f64_i32_32(double %dbl) { 704; CHECK-LABEL: fcvtzs_sat_f64_i32_32: 705; CHECK: // %bb.0: 706; CHECK-NEXT: fcvtzs w0, d0, #32 707; CHECK-NEXT: ret 708 %fix = fmul double %dbl, 4294967296.0 709 %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix) 710 ret i32 %cvt 711} 712 713define i64 @fcvtzs_sat_f64_i64_7(double %dbl) { 714; CHECK-LABEL: fcvtzs_sat_f64_i64_7: 715; CHECK: // %bb.0: 716; CHECK-NEXT: fcvtzs x0, d0, #7 717; CHECK-NEXT: ret 718 %fix = fmul double %dbl, 128.0 719 %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix) 720 ret i64 %cvt 721} 722 723define i64 @fcvtzs_sat_f64_i64_64(double %dbl) { 724; CHECK-LABEL: fcvtzs_sat_f64_i64_64: 725; CHECK: // %bb.0: 726; CHECK-NEXT: fcvtzs x0, d0, #64 727; CHECK-NEXT: ret 728 %fix = fmul double %dbl, 18446744073709551616.0 729 %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix) 730 ret i64 %cvt 731} 732 733define i32 @fcvtzs_sat_f16_i32_7(half %dbl) { 734; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_7: 735; CHECK-NO16: // %bb.0: 736; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24 737; CHECK-NO16-NEXT: fcvt s0, h0 738; CHECK-NO16-NEXT: fmul s0, s0, s1 739; CHECK-NO16-NEXT: fcvt h0, s0 740; CHECK-NO16-NEXT: fcvt s0, h0 741; CHECK-NO16-NEXT: fcvtzs w0, s0 742; CHECK-NO16-NEXT: ret 743; 744; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_7: 745; CHECK-FP16: // %bb.0: 746; CHECK-FP16-NEXT: fcvtzs w0, h0, #7 747; CHECK-FP16-NEXT: ret 748 %fix = fmul half %dbl, 128.0 749 %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix) 750 ret i32 %cvt 751} 752 753define i32 @fcvtzs_sat_f16_i32_15(half %dbl) { 754; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_15: 755; CHECK-NO16: // %bb.0: 756; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24 757; CHECK-NO16-NEXT: fcvt s0, h0 758; CHECK-NO16-NEXT: fmul s0, s0, s1 759; CHECK-NO16-NEXT: fcvt h0, s0 760; CHECK-NO16-NEXT: fcvt s0, h0 761; CHECK-NO16-NEXT: fcvtzs w0, s0 762; CHECK-NO16-NEXT: ret 763; 764; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_15: 765; CHECK-FP16: // %bb.0: 766; CHECK-FP16-NEXT: fcvtzs w0, h0, #15 767; CHECK-FP16-NEXT: ret 768 %fix = fmul half %dbl, 32768.0 769 %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix) 770 ret i32 %cvt 771} 772 773define i64 @fcvtzs_sat_f16_i64_7(half %dbl) { 774; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_7: 775; CHECK-NO16: // %bb.0: 776; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24 777; CHECK-NO16-NEXT: fcvt s0, h0 778; CHECK-NO16-NEXT: fmul s0, s0, s1 779; CHECK-NO16-NEXT: fcvt h0, s0 780; CHECK-NO16-NEXT: fcvt s0, h0 781; CHECK-NO16-NEXT: fcvtzs x0, s0 782; CHECK-NO16-NEXT: ret 783; 784; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_7: 785; CHECK-FP16: // %bb.0: 786; CHECK-FP16-NEXT: fcvtzs x0, h0, #7 787; CHECK-FP16-NEXT: ret 788 %fix = fmul half %dbl, 128.0 789 %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix) 790 ret i64 %cvt 791} 792 793define i64 @fcvtzs_sat_f16_i64_15(half %dbl) { 794; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_15: 795; CHECK-NO16: // %bb.0: 796; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24 797; CHECK-NO16-NEXT: fcvt s0, h0 798; CHECK-NO16-NEXT: fmul s0, s0, s1 799; CHECK-NO16-NEXT: fcvt h0, s0 800; CHECK-NO16-NEXT: fcvt s0, h0 801; CHECK-NO16-NEXT: fcvtzs x0, s0 802; CHECK-NO16-NEXT: ret 803; 804; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_15: 805; CHECK-FP16: // %bb.0: 806; CHECK-FP16-NEXT: fcvtzs x0, h0, #15 807; CHECK-FP16-NEXT: ret 808 %fix = fmul half %dbl, 32768.0 809 %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix) 810 ret i64 %cvt 811} 812 813; fptoui 814 815declare i32 @llvm.fptoui.sat.i32.f32(float) 816declare i64 @llvm.fptoui.sat.i64.f32(float) 817declare i32 @llvm.fptoui.sat.i32.f64(double) 818declare i64 @llvm.fptoui.sat.i64.f64(double) 819declare i32 @llvm.fptoui.sat.i32.f16(half) 820declare i64 @llvm.fptoui.sat.i64.f16(half) 821 822define i32 @fcvtzu_sat_f32_i32_7(float %flt) { 823; CHECK-LABEL: fcvtzu_sat_f32_i32_7: 824; CHECK: // %bb.0: 825; CHECK-NEXT: fcvtzu w0, s0, #7 826; CHECK-NEXT: ret 827 %fix = fmul float %flt, 128.0 828 %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix) 829 ret i32 %cvt 830} 831 832define i32 @fcvtzu_sat_f32_i32_32(float %flt) { 833; CHECK-LABEL: fcvtzu_sat_f32_i32_32: 834; CHECK: // %bb.0: 835; CHECK-NEXT: fcvtzu w0, s0, #32 836; CHECK-NEXT: ret 837 %fix = fmul float %flt, 4294967296.0 838 %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix) 839 ret i32 %cvt 840} 841 842define i64 @fcvtzu_sat_f32_i64_64(float %flt) { 843; CHECK-LABEL: fcvtzu_sat_f32_i64_64: 844; CHECK: // %bb.0: 845; CHECK-NEXT: fcvtzu x0, s0, #64 846; CHECK-NEXT: ret 847 %fix = fmul float %flt, 18446744073709551616.0 848 %cvt = call i64 @llvm.fptoui.sat.i64.f32(float %fix) 849 ret i64 %cvt 850} 851 852define i32 @fcvtzu_sat_f64_i32_7(double %dbl) { 853; CHECK-LABEL: fcvtzu_sat_f64_i32_7: 854; CHECK: // %bb.0: 855; CHECK-NEXT: fcvtzu w0, d0, #7 856; CHECK-NEXT: ret 857 %fix = fmul double %dbl, 128.0 858 %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix) 859 ret i32 %cvt 860} 861 862define i32 @fcvtzu_sat_f64_i32_32(double %dbl) { 863; CHECK-LABEL: fcvtzu_sat_f64_i32_32: 864; CHECK: // %bb.0: 865; CHECK-NEXT: fcvtzu w0, d0, #32 866; CHECK-NEXT: ret 867 %fix = fmul double %dbl, 4294967296.0 868 %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix) 869 ret i32 %cvt 870} 871 872define i64 @fcvtzu_sat_f64_i64_7(double %dbl) { 873; CHECK-LABEL: fcvtzu_sat_f64_i64_7: 874; CHECK: // %bb.0: 875; CHECK-NEXT: fcvtzu x0, d0, #7 876; CHECK-NEXT: ret 877 %fix = fmul double %dbl, 128.0 878 %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix) 879 ret i64 %cvt 880} 881 882define i64 @fcvtzu_sat_f64_i64_64(double %dbl) { 883; CHECK-LABEL: fcvtzu_sat_f64_i64_64: 884; CHECK: // %bb.0: 885; CHECK-NEXT: fcvtzu x0, d0, #64 886; CHECK-NEXT: ret 887 %fix = fmul double %dbl, 18446744073709551616.0 888 %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix) 889 ret i64 %cvt 890} 891 892define i32 @fcvtzu_sat_f16_i32_7(half %dbl) { 893; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_7: 894; CHECK-NO16: // %bb.0: 895; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24 896; CHECK-NO16-NEXT: fcvt s0, h0 897; CHECK-NO16-NEXT: fmul s0, s0, s1 898; CHECK-NO16-NEXT: fcvt h0, s0 899; CHECK-NO16-NEXT: fcvt s0, h0 900; CHECK-NO16-NEXT: fcvtzu w0, s0 901; CHECK-NO16-NEXT: ret 902; 903; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_7: 904; CHECK-FP16: // %bb.0: 905; CHECK-FP16-NEXT: fcvtzu w0, h0, #7 906; CHECK-FP16-NEXT: ret 907 %fix = fmul half %dbl, 128.0 908 %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix) 909 ret i32 %cvt 910} 911 912define i32 @fcvtzu_sat_f16_i32_15(half %dbl) { 913; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_15: 914; CHECK-NO16: // %bb.0: 915; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24 916; CHECK-NO16-NEXT: fcvt s0, h0 917; CHECK-NO16-NEXT: fmul s0, s0, s1 918; CHECK-NO16-NEXT: fcvt h0, s0 919; CHECK-NO16-NEXT: fcvt s0, h0 920; CHECK-NO16-NEXT: fcvtzu w0, s0 921; CHECK-NO16-NEXT: ret 922; 923; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_15: 924; CHECK-FP16: // %bb.0: 925; CHECK-FP16-NEXT: fcvtzu w0, h0, #15 926; CHECK-FP16-NEXT: ret 927 %fix = fmul half %dbl, 32768.0 928 %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix) 929 ret i32 %cvt 930} 931 932define i64 @fcvtzu_sat_f16_i64_7(half %dbl) { 933; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_7: 934; CHECK-NO16: // %bb.0: 935; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24 936; CHECK-NO16-NEXT: fcvt s0, h0 937; CHECK-NO16-NEXT: fmul s0, s0, s1 938; CHECK-NO16-NEXT: fcvt h0, s0 939; CHECK-NO16-NEXT: fcvt s0, h0 940; CHECK-NO16-NEXT: fcvtzu x0, s0 941; CHECK-NO16-NEXT: ret 942; 943; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_7: 944; CHECK-FP16: // %bb.0: 945; CHECK-FP16-NEXT: fcvtzu x0, h0, #7 946; CHECK-FP16-NEXT: ret 947 %fix = fmul half %dbl, 128.0 948 %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix) 949 ret i64 %cvt 950} 951 952define i64 @fcvtzu_sat_f16_i64_15(half %dbl) { 953; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_15: 954; CHECK-NO16: // %bb.0: 955; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24 956; CHECK-NO16-NEXT: fcvt s0, h0 957; CHECK-NO16-NEXT: fmul s0, s0, s1 958; CHECK-NO16-NEXT: fcvt h0, s0 959; CHECK-NO16-NEXT: fcvt s0, h0 960; CHECK-NO16-NEXT: fcvtzu x0, s0 961; CHECK-NO16-NEXT: ret 962; 963; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_15: 964; CHECK-FP16: // %bb.0: 965; CHECK-FP16-NEXT: fcvtzu x0, h0, #15 966; CHECK-FP16-NEXT: ret 967 %fix = fmul half %dbl, 32768.0 968 %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix) 969 ret i64 %cvt 970} 971