Lines Matching refs:flt

7 define i32 @fcvtzs_f32_i32_7(float %flt) {
12   %fix = fmul float %flt, 128.0
17 define i32 @fcvtzs_f32_i32_32(float %flt) {
22   %fix = fmul float %flt, 4294967296.0
27 define i64 @fcvtzs_f32_i64_7(float %flt) {
32   %fix = fmul float %flt, 128.0
37 define i64 @fcvtzs_f32_i64_64(float %flt) {
42   %fix = fmul float %flt, 18446744073709551616.0
87 define i32 @fcvtzs_f16_i32_7(half %flt) {
102   %fix = fmul half %flt, 128.0
107 define i32 @fcvtzs_f16_i32_15(half %flt) {
122   %fix = fmul half %flt, 32768.0
127 define i64 @fcvtzs_f16_i64_7(half %flt) {
142   %fix = fmul half %flt, 128.0
147 define i64 @fcvtzs_f16_i64_15(half %flt) {
162   %fix = fmul half %flt, 32768.0
169 define i32 @fcvtzu_f32_i32_7(float %flt) {
174   %fix = fmul float %flt, 128.0
179 define i32 @fcvtzu_f32_i32_32(float %flt) {
184   %fix = fmul float %flt, 4294967296.0
189 define i64 @fcvtzu_f32_i64_7(float %flt) {
194   %fix = fmul float %flt, 128.0
199 define i64 @fcvtzu_f32_i64_64(float %flt) {
204   %fix = fmul float %flt, 18446744073709551616.0
249 define i32 @fcvtzu_f16_i32_7(half %flt) {
264   %fix = fmul half %flt, 128.0
269 define i32 @fcvtzu_f16_i32_15(half %flt) {
284   %fix = fmul half %flt, 32768.0
289 define i64 @fcvtzu_f16_i64_7(half %flt) {
304   %fix = fmul half %flt, 128.0
309 define i64 @fcvtzu_f16_i64_15(half %flt) {
324   %fix = fmul half %flt, 32768.0
663 define i32 @fcvtzs_sat_f32_i32_7(float %flt) {
668   %fix = fmul float %flt, 128.0
673 define i32 @fcvtzs_sat_f32_i32_32(float %flt) {
678   %fix = fmul float %flt, 4294967296.0
683 define i64 @fcvtzs_sat_f32_i64_64(float %flt) {
688   %fix = fmul float %flt, 18446744073709551616.0
822 define i32 @fcvtzu_sat_f32_i32_7(float %flt) {
827   %fix = fmul float %flt, 128.0
832 define i32 @fcvtzu_sat_f32_i32_32(float %flt) {
837   %fix = fmul float %flt, 4294967296.0
842 define i64 @fcvtzu_sat_f32_i64_64(float %flt) {
847   %fix = fmul float %flt, 18446744073709551616.0