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/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmips-fpu-instructions.s30 abs.d $f12,$f14
34 floor.w.d $f12,$f14
36 ceil.w.d $f12,$f14
40 neg.d $f12,$f14
42 round.w.d $f12,$f14
44 sqrt.d $f12,$f14
48 trunc.w.d $f12,$f14
88 c.eq.d $f12,$f14
134 cvt.d.w $f12,$f14
135 cvt.s.d $f12,$f14
[all …]
H A Dmicromips-fpu-instructions.s393 c.f.d $f12, $f14
394 c.un.d $f12, $f14
395 c.eq.d $f12, $f14
396 c.ueq.d $f12, $f14
397 c.olt.d $f12, $f14
398 c.ult.d $f12, $f14
399 c.ole.d $f12, $f14
400 c.ule.d $f12, $f14
401 c.sf.d $f12, $f14
402 c.ngle.d $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dselect-flt.ll76 ; M3-NEXT: mov.s $f0, $f14
83 ; CMOV64-NEXT: mov.s $f0, $f14
121 ; M2-NEXT: mov.s $f0, $f14
191 ; M2-NEXT: c.olt.s $f12, $f14
196 ; M2-NEXT: mov.s $f0, $f14
272 ; M2-NEXT: mov.s $f0, $f14
348 ; M2-NEXT: mov.s $f0, $f14
424 ; M2-NEXT: mov.s $f0, $f14
495 ; M2-NEXT: c.eq.s $f12, $f14
500 ; M2-NEXT: mov.s $f0, $f14
[all …]
H A Dselect-dbl.ll82 ; M3-NEXT: mov.d $f0, $f14
89 ; CMOV64-NEXT: mov.d $f0, $f14
130 ; M2-NEXT: mov.d $f0, $f14
205 ; M2-NEXT: c.olt.d $f12, $f14
210 ; M2-NEXT: mov.d $f0, $f14
292 ; M2-NEXT: mov.d $f0, $f14
374 ; M2-NEXT: mov.d $f0, $f14
456 ; M2-NEXT: mov.d $f0, $f14
533 ; M2-NEXT: c.eq.d $f12, $f14
538 ; M2-NEXT: mov.d $f0, $f14
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dfcmp.ll41 ; 32-C-DAG: c.eq.s $f12, $f14
58 ; MM32R3-DAG: c.eq.s $f12, $f14
74 ; 32-C-DAG: c.ule.s $f12, $f14
91 ; MM32R3-DAG: c.ule.s $f12, $f14
107 ; 32-C-DAG: c.ult.s $f12, $f14
124 ; MM32R3-DAG: c.ult.s $f12, $f14
140 ; 32-C-DAG: c.olt.s $f12, $f14
157 ; MM32R3-DAG: c.olt.s $f12, $f14
173 ; 32-C-DAG: c.ole.s $f12, $f14
190 ; MM32R3-DAG: c.ole.s $f12, $f14
[all …]
H A Dfmadd1.ll37 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
48 ; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
77 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
123 ; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
136 ; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
142 ; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
181 ; 64-NONAN: nmsub.s $f0, $f14, $f12, $f13
305 ; 64-NONAN: nmadd.d $f0, $f14, $f12, $f13
311 ; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
353 ; 64-NONAN: nmsub.d $f0, $f14, $f12, $f13
[all …]
H A Dnmadd.ll18 ; CHECK-NM-64: nmadd.s $f0, $f14, $f12, $f13
19 ; CHECK-NM: nmadd.s $f0, $f0, $f12, $f14
23 ; CHECK-NOT-NM: mul.s $f0, $f12, $f14
36 ; CHECK-NM-64: nmadd.d $f0, $f14, $f12, $f13
37 ; CHECK-NM: nmadd.d $f0, $f0, $f12, $f14
41 ; CHECK-NOT-NM: mul.d $f0, $f12, $f14
54 ; CHECK-NM-64: nmsub.s $f0, $f14, $f12, $f13
55 ; CHECK-NM: nmsub.s $f0, $f0, $f12, $f14
59 ; CHECK-NOT-NM: mul.s $f0, $f12, $f14
73 ; CHECK-NM: nmsub.d $f0, $f0, $f12, $f14
[all …]
H A Dselect.ll205 ; 64-NEXT: mov.s $f0, $f14
211 ; 64R2-NEXT: mov.s $f0, $f14
258 ; 64-NEXT: mov.d $f0, $f14
284 ; 32-NEXT: mov.s $f0, $f14
336 ; 32-NEXT: mov.s $f0, $f14
388 ; 32-NEXT: mov.s $f0, $f14
440 ; 32-NEXT: mov.d $f0, $f14
496 ; 32-NEXT: mov.d $f0, $f14
552 ; 32-NEXT: mov.d $f0, $f14
608 ; 32-NEXT: mov.d $f0, $f14
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfloat_arithmetic_operations.mir23 liveins: $f12, $f14
26 ; FP32: liveins: $f12, $f14
33 ; FP64: liveins: $f12, $f14
40 %1:_(s32) = COPY $f14
52 liveins: $f12, $f14
55 ; FP32: liveins: $f12, $f14
69 %1:_(s32) = COPY $f14
81 liveins: $f12, $f14
98 %1:_(s32) = COPY $f14
110 liveins: $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dfloat_arithmetic_operations.mir24 liveins: $f12, $f14
27 ; FP32: liveins: $f12, $f14
34 ; FP64: liveins: $f12, $f14
41 %1:fprb(s32) = COPY $f14
55 liveins: $f12, $f14
58 ; FP32: liveins: $f12, $f14
72 %1:fprb(s32) = COPY $f14
86 liveins: $f12, $f14
103 %1:fprb(s32) = COPY $f14
117 liveins: $f12, $f14
[all …]
H A Dfcmp.mir49 liveins: $f12, $f14
75 liveins: $f12, $f14
101 liveins: $f12, $f14
137 liveins: $f12, $f14
173 liveins: $f12, $f14
209 liveins: $f12, $f14
245 liveins: $f12, $f14
281 liveins: $f12, $f14
317 liveins: $f12, $f14
353 liveins: $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfloat_arithmetic_operations.mir24 liveins: $f12, $f14
27 ; FP32: liveins: $f12, $f14
34 ; FP64: liveins: $f12, $f14
41 %1:_(s32) = COPY $f14
54 liveins: $f12, $f14
57 ; FP32: liveins: $f12, $f14
71 %1:_(s32) = COPY $f14
84 liveins: $f12, $f14
101 %1:_(s32) = COPY $f14
114 liveins: $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32/
H A Dvalid-mips32-el.txt2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
25 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
27 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
29 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
31 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
33 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
35 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
39 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
47 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
[all …]
H A Dvalid-mips32.txt217 0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22
226 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
227 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
228 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
235 0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14
243 0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
244 0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
245 0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
251 0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
255 0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r5/
H A Dvalid-mips32r5-el.txt3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
25 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
27 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
29 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
31 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
33 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
35 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
39 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
47 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
[all …]
H A Dvalid-mips32r5.txt230 0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22
239 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
240 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
241 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
249 0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14
257 0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
258 0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
259 0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
265 0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
269 0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r3/
H A Dvalid-mips32r3-el.txt3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
25 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
27 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
29 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
31 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
33 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
35 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
39 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
47 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
[all …]
H A Dvalid-mips32r3.txt229 0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22
238 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
239 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
240 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
248 0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14
256 0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
257 0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
258 0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
264 0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
268 0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r2/
H A Dvalid-mips32r2-el.txt6 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
9 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
28 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
30 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
32 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
34 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
36 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
38 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
42 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
50 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dfcmp.ll33 ; CHECK-NEXT: c.un.s $f12, $f14
45 ; CHECK-NEXT: c.un.s $f12, $f14
59 ; CHECK-NEXT: c.eq.s $f12, $f14
71 ; CHECK-NEXT: c.eq.s $f12, $f14
85 ; CHECK-NEXT: c.ueq.s $f12, $f14
97 ; CHECK-NEXT: c.ueq.s $f12, $f14
111 ; CHECK-NEXT: c.olt.s $f12, $f14
123 ; CHECK-NEXT: c.olt.s $f12, $f14
137 ; CHECK-NEXT: c.ult.s $f12, $f14
237 ; CHECK-NEXT: c.un.d $f12, $f14
[all …]
H A Dfloat_arithmetic_operations.ll10 ; CHECK-NEXT: add.s $f0, $f12, $f14
21 ; CHECK-NEXT: sub.s $f0, $f12, $f14
32 ; CHECK-NEXT: mul.s $f0, $f12, $f14
43 ; CHECK-NEXT: div.s $f0, $f12, $f14
54 ; CHECK-NEXT: add.d $f0, $f12, $f14
65 ; CHECK-NEXT: sub.d $f0, $f12, $f14
76 ; CHECK-NEXT: mul.d $f0, $f12, $f14
87 ; CHECK-NEXT: div.d $f0, $f12, $f14
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-mips64r3-el.txt3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
7 0x00 0x71 0xda 0x46 # CHECK: add.ps $f4, $f14, $f26
26 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
28 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
30 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
32 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
34 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
36 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
48 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r5/
H A Dvalid-mips64r5-el.txt3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
7 0x00 0x71 0xda 0x46 # CHECK: add.ps $f4, $f14, $f26
26 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
28 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
30 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
32 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
34 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
36 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
48 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-mips64r2-el.txt6 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
9 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
29 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
31 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
33 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
35 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
37 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
39 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
51 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
96 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-el.txt2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
45 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
53 0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
[all …]

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