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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-ld2.mir18 ; CHECK: $d0 = COPY %dst1
23 $d0 = COPY %dst1(<8 x s8>)
41 ; CHECK: $q0 = COPY %dst1
46 $q0 = COPY %dst1(<16 x s8>)
64 ; CHECK: $d0 = COPY %dst1
87 ; CHECK: $q0 = COPY %dst1
110 ; CHECK: $d0 = COPY %dst1
133 ; CHECK: $q0 = COPY %dst1
156 ; CHECK: $q0 = COPY %dst1
207 $d0 = COPY %dst1(s64)
[all …]
H A Dselect-ld4.mir20 ; CHECK: $d0 = COPY %dst1
27 $d0 = COPY %dst1(<8 x s8>)
49 ; CHECK: $q0 = COPY %dst1
56 $q0 = COPY %dst1(<16 x s8>)
78 ; CHECK: $d0 = COPY %dst1
107 ; CHECK: $q0 = COPY %dst1
136 ; CHECK: $d0 = COPY %dst1
165 ; CHECK: $q0 = COPY %dst1
194 ; CHECK: $q0 = COPY %dst1
259 $d0 = COPY %dst1(s64)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/MemCpyOpt/
H A Dmemset-memcpy-to-2x-memset.ll6 define void @test(i8* %dst1, i8* %dst2, i8 %c) {
12 call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i1 false)
17 define void @test_smaller_memcpy(i8* %dst1, i8* %dst2, i8 %c) {
23 call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i1 false)
28 define void @test_smaller_memset(i8* %dst1, i8* %dst2, i8 %c) {
34 call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 100, i1 false)
39 define void @test_align_memset(i8* %dst1, i8* %dst2, i8 %c) {
50 define void @test_different_types(i8* %dst1, i8* %dst2, i8 %c) {
61 define void @test_different_types_2(i8* %dst1, i8* %dst2, i8 %c) {
72 define void @test_different_source_gep(i8* %dst1, i8* %dst2, i8 %c) {
[all …]
H A Dvariable-sized-memset-memcpy.ll13 %dst1 = alloca i8, i64 %size
15 call void @llvm.memset.p0i8.i64(i8* align 8 %dst1, i8 %c, i64 %size, i1 false)
16 call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %dst2, i8* align 8 %dst1, i64 %size, i1 false)
30 %dst1 = alloca i8, i64 %size1
32 call void @llvm.memset.p0i8.i64(i8* align 8 %dst1, i8 %c, i64 %size1, i1 false)
33 call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %dst2, i8* align 8 %dst1, i64 %size2, i1 false)
H A Dinvariant.start.ll38 define void @test2(i8* %dst1, i8* %dst2, i8 %c) {
45 call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i1 false)
46 %i = call {}* @llvm.invariant.start.p0i8(i64 32, i8* %dst1)
47 call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %dst2, i8* align 8 %dst1, i64 128, i1 false)
/llvm-project-15.0.7/llvm/test/MC/M68k/Relocations/
H A Ddata-pc-rel.s6 ; RELOC: R_68K_PC8 dst1 0x1
7 ; INSTR: move.l (dst1,%pc,%a0), %a0
8 ; FIXUP: fixup A - offset: 3, value: dst1+1, kind: FK_PCRel_1
9 move.l (dst1,%pc,%a0), %a0
H A Ddata-gotpcrel.s6 ; RELOC: R_68K_GOTPCREL8 dst1 0x1
7 ; INSTR: move.l (dst1@GOTPCREL,%pc,%d0), %a0
8 ; FIXUP: fixup A - offset: 3, value: dst1@GOTPCREL+1, kind: FK_PCRel_1
9 move.l (dst1@GOTPCREL,%pc,%d0), %a0
H A Ddata-gotoff.s6 ; RELOC: R_68K_GOTOFF8 dst1 0x0
7 ; INSTR: move.l (dst1@GOTOFF,%a5,%d0), %d0
8 ; FIXUP: fixup A - offset: 3, value: dst1@GOTOFF, kind: FK_Data_1
9 move.l (dst1@GOTOFF,%a5,%d0), %d0
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dlcomm.s3 # CHECK: 00000000 l O .sbss.1 00000001 dst1
12 .lcomm dst1,1,1,1
17 r0 = add(pc, ##dst1@PCREL)
/llvm-project-15.0.7/libc/test/src/__support/File/
H A Dfile_test.cpp138 dst1(f->get_str(), sizeof(data) * 2); in TEST() local
139 EXPECT_MEM_EQ(src1, dst1); in TEST()
171 MemoryView src1("hello\n", 6), dst1(f_line->get_str(), 6); in TEST() local
172 EXPECT_MEM_EQ(src1, dst1); in TEST()
244 MemoryView src1(initial_content, READ_SIZE), dst1(read_data, READ_SIZE); in TEST() local
245 EXPECT_MEM_EQ(src1, dst1); in TEST()
364 MemoryView src1(initial_content, READ_SIZE), dst1(read_data, READ_SIZE); in TEST() local
365 EXPECT_MEM_EQ(src1, dst1); in TEST()
401 dst1(f->get_str(), sizeof(initial_content)); in TEST() local
402 EXPECT_MEM_EQ(src1, dst1); in TEST()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfree-zext.ll16 define void @test_free_zext2(i32* %ptr, i32* %dst1, i64* %dst2) {
25 store i32 %load16, i32* %dst1, align 4
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Difcvt-iter-indbr.ll72 %dst1 = call i8* @bar(i32 1, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
87 indirectbr i8* %dst1, [label %bb1, label %bb2]
/llvm-project-15.0.7/libc/test/src/stdio/
H A Dfopencookie_test.cpp211 MemoryView src1(INITIAL_CONTENT, READ_SIZE), dst1(read_data, READ_SIZE); in TEST() local
212 EXPECT_MEM_EQ(src1, dst1); in TEST()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dxor-of-icmps-with-extra-uses.ll58 define i1 @v3_branch(i32 %X, i32* %dst0, i32* %dst1) {
82 store i32 0, i32* %dst1
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td2148 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2151 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2154 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2157 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2160 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2184 : VLDU_G_ELE_V2<"v2.u8 \t{{$dst1, $dst2}}, [$src];", Int16Regs>;
2269 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2272 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2275 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2278 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
[all …]
H A DNVPTXInstrInfo.td2479 (outs regclass:$dst1, regclass:$dst2),
2483 "\t{{$dst1, $dst2}}, [$addr];", []>;
2485 (outs regclass:$dst1, regclass:$dst2),
2489 "\t{{$dst1, $dst2}}, [$addr];", []>;
2491 (outs regclass:$dst1, regclass:$dst2),
2495 "\t{{$dst1, $dst2}}, [$addr];", []>;
2497 (outs regclass:$dst1, regclass:$dst2),
2501 "\t{{$dst1, $dst2}}, [$addr+$offset];", []>;
2503 (outs regclass:$dst1, regclass:$dst2),
2507 "\t{{$dst1, $dst2}}, [$addr+$offset];", []>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td511 def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
513 "ladd $dst2, $dst1, $src1, $src2, $src3",
516 def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
518 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
520 def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
522 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
527 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
529 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td358 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),
359 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Instructions.td371 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
373 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
377 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
379 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td1498 def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
1499 !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1503 def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
1504 !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
H A DX86InstrInfo.td2126 let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in {
2127 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2),
2130 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2),
2134 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2),
2138 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2),
2157 let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2",
2159 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2),
2162 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2),
2165 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2),
2168 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2),
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCondMov.td303 PseudoSE<(outs RC:$dst1, RC:$dst2),
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dx86-cmov-converter.ll1047 %dst1 = select i1 %cmp1, ptr %gep1, ptr %begin_dup
1048 store i32 %data, ptr%dst1, align 4
1049 %gep2 = getelementptr inbounds i32, ptr%dst1, i64 2
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrVFP.td1307 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
1308 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
1313 bits<5> dst1;
1318 let Inst{3-0} = dst1{4-1};
1319 let Inst{5} = dst1{0};
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dlower-mem-intrinsics.ll261 … @memcpy_multi_use_one_function(i8 addrspace(1)* %dst0, i8 addrspace(1)* %dst1, i8 addrspace(1)* %…
330 …call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* %dst1, i8 addrspace(1)* %src, i64 %m, i1 fal…
375 …lti_use_one_function_keep_small(i8 addrspace(1)* %dst0, i8 addrspace(1)* %dst1, i8 addrspace(1)* %…
473 …call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* %dst1, i8 addrspace(1)* %src, i64 102, i1 fa…

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