1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3...
4---
5name:            LD2Twov8b
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $x0, $x1, $x2
12    ; CHECK-LABEL: name: LD2Twov8b
13    ; CHECK: liveins: $x0, $x1, $x2
14    ; CHECK: %ptr:gpr64sp = COPY $x0
15    ; CHECK: [[LD2Twov8b:%[0-9]+]]:dd = LD2Twov8b %ptr :: (load (<8 x s64>))
16    ; CHECK: %dst1:fpr64 = COPY [[LD2Twov8b]].dsub0
17    ; CHECK: %dst2:fpr64 = COPY [[LD2Twov8b]].dsub1
18    ; CHECK: $d0 = COPY %dst1
19    ; CHECK: $d1 = COPY %dst2
20    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1
21    %ptr:gpr(p0) = COPY $x0
22    %dst1:fpr(<8 x s8>), %dst2:fpr(<8 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<8 x s64>))
23    $d0 = COPY %dst1(<8 x s8>)
24    $d1 = COPY %dst2(<8 x s8>)
25    RET_ReallyLR implicit $d0, implicit $d1
26...
27---
28name:            LD2Twov16b
29legalized:       true
30regBankSelected: true
31tracksRegLiveness: true
32body:             |
33  bb.0:
34    liveins: $x0, $x1, $x2
35    ; CHECK-LABEL: name: LD2Twov16b
36    ; CHECK: liveins: $x0, $x1, $x2
37    ; CHECK: %ptr:gpr64sp = COPY $x0
38    ; CHECK: [[LD2Twov16b:%[0-9]+]]:qq = LD2Twov16b %ptr :: (load (<16 x s64>))
39    ; CHECK: %dst1:fpr128 = COPY [[LD2Twov16b]].qsub0
40    ; CHECK: %dst2:fpr128 = COPY [[LD2Twov16b]].qsub1
41    ; CHECK: $q0 = COPY %dst1
42    ; CHECK: $q1 = COPY %dst2
43    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1
44    %ptr:gpr(p0) = COPY $x0
45    %dst1:fpr(<16 x s8>), %dst2:fpr(<16 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<16 x s64>))
46    $q0 = COPY %dst1(<16 x s8>)
47    $q1 = COPY %dst2(<16 x s8>)
48    RET_ReallyLR implicit $q0, implicit $q1
49...
50---
51name:            LD2Twov4h
52legalized:       true
53regBankSelected: true
54tracksRegLiveness: true
55body:             |
56  bb.0:
57    liveins: $x0, $x1, $x2
58    ; CHECK-LABEL: name: LD2Twov4h
59    ; CHECK: liveins: $x0, $x1, $x2
60    ; CHECK: %ptr:gpr64sp = COPY $x0
61    ; CHECK: [[LD2Twov4h:%[0-9]+]]:dd = LD2Twov4h %ptr :: (load (<4 x s64>))
62    ; CHECK: %dst1:fpr64 = COPY [[LD2Twov4h]].dsub0
63    ; CHECK: %dst2:fpr64 = COPY [[LD2Twov4h]].dsub1
64    ; CHECK: $d0 = COPY %dst1
65    ; CHECK: $d1 = COPY %dst2
66    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1
67    %ptr:gpr(p0) = COPY $x0
68    %dst1:fpr(<4 x s16>), %dst2:fpr(<4 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<4 x s64>))
69    $d0 = COPY %dst1(<4 x s16>)
70    $d1 = COPY %dst2(<4 x s16>)
71    RET_ReallyLR implicit $d0, implicit $d1
72...
73---
74name:            LD2Twov8h
75legalized:       true
76regBankSelected: true
77tracksRegLiveness: true
78body:             |
79  bb.0:
80    liveins: $x0, $x1, $x2
81    ; CHECK-LABEL: name: LD2Twov8h
82    ; CHECK: liveins: $x0, $x1, $x2
83    ; CHECK: %ptr:gpr64sp = COPY $x0
84    ; CHECK: [[LD2Twov8h:%[0-9]+]]:qq = LD2Twov8h %ptr :: (load (<8 x s64>))
85    ; CHECK: %dst1:fpr128 = COPY [[LD2Twov8h]].qsub0
86    ; CHECK: %dst2:fpr128 = COPY [[LD2Twov8h]].qsub1
87    ; CHECK: $q0 = COPY %dst1
88    ; CHECK: $q1 = COPY %dst2
89    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1
90    %ptr:gpr(p0) = COPY $x0
91    %dst1:fpr(<8 x s16>), %dst2:fpr(<8 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<8 x s64>))
92    $q0 = COPY %dst1(<8 x s16>)
93    $q1 = COPY %dst2(<8 x s16>)
94    RET_ReallyLR implicit $q0, implicit $q1
95...
96---
97name:            LD2Twov2s
98legalized:       true
99regBankSelected: true
100tracksRegLiveness: true
101body:             |
102  bb.0:
103    liveins: $x0, $x1, $x2
104    ; CHECK-LABEL: name: LD2Twov2s
105    ; CHECK: liveins: $x0, $x1, $x2
106    ; CHECK: %ptr:gpr64sp = COPY $x0
107    ; CHECK: [[LD2Twov2s:%[0-9]+]]:dd = LD2Twov2s %ptr :: (load (<2 x s64>))
108    ; CHECK: %dst1:fpr64 = COPY [[LD2Twov2s]].dsub0
109    ; CHECK: %dst2:fpr64 = COPY [[LD2Twov2s]].dsub1
110    ; CHECK: $d0 = COPY %dst1
111    ; CHECK: $d1 = COPY %dst2
112    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1
113    %ptr:gpr(p0) = COPY $x0
114    %dst1:fpr(<2 x s32>), %dst2:fpr(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x s64>))
115    $d0 = COPY %dst1(<2 x s32>)
116    $d1 = COPY %dst2(<2 x s32>)
117    RET_ReallyLR implicit $d0, implicit $d1
118...
119---
120name:            LD2Twov4s
121legalized:       true
122regBankSelected: true
123tracksRegLiveness: true
124body:             |
125  bb.0:
126    liveins: $x0, $x1, $x2
127    ; CHECK-LABEL: name: LD2Twov4s
128    ; CHECK: liveins: $x0, $x1, $x2
129    ; CHECK: %ptr:gpr64sp = COPY $x0
130    ; CHECK: [[LD2Twov4s:%[0-9]+]]:qq = LD2Twov4s %ptr :: (load (<4 x s64>))
131    ; CHECK: %dst1:fpr128 = COPY [[LD2Twov4s]].qsub0
132    ; CHECK: %dst2:fpr128 = COPY [[LD2Twov4s]].qsub1
133    ; CHECK: $q0 = COPY %dst1
134    ; CHECK: $q1 = COPY %dst2
135    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1
136    %ptr:gpr(p0) = COPY $x0
137    %dst1:fpr(<4 x s32>), %dst2:fpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<4 x s64>))
138    $q0 = COPY %dst1(<4 x s32>)
139    $q1 = COPY %dst2(<4 x s32>)
140    RET_ReallyLR implicit $q0, implicit $q1
141...
142---
143name:            LD2Twov2d_s64
144legalized:       true
145regBankSelected: true
146tracksRegLiveness: true
147body:             |
148  bb.0:
149    liveins: $x0, $x1, $x2
150    ; CHECK-LABEL: name: LD2Twov2d_s64
151    ; CHECK: liveins: $x0, $x1, $x2
152    ; CHECK: %ptr:gpr64sp = COPY $x0
153    ; CHECK: [[LD2Twov2d:%[0-9]+]]:qq = LD2Twov2d %ptr :: (load (<2 x s64>))
154    ; CHECK: %dst1:fpr128 = COPY [[LD2Twov2d]].qsub0
155    ; CHECK: %dst2:fpr128 = COPY [[LD2Twov2d]].qsub1
156    ; CHECK: $q0 = COPY %dst1
157    ; CHECK: $q1 = COPY %dst2
158    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1
159    %ptr:gpr(p0) = COPY $x0
160    %dst1:fpr(<2 x s64>), %dst2:fpr(<2 x s64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x s64>))
161    $q0 = COPY %dst1(<2 x s64>)
162    $q1 = COPY %dst2(<2 x s64>)
163    RET_ReallyLR implicit $q0, implicit $q1
164...
165---
166name:            LD2Twov2d_p0
167legalized:       true
168regBankSelected: true
169tracksRegLiveness: true
170body:             |
171  bb.0:
172    liveins: $x0, $x1, $x2
173    ; CHECK-LABEL: name: LD2Twov2d_p0
174    ; CHECK: liveins: $x0, $x1, $x2
175    ; CHECK: %ptr:gpr64sp = COPY $x0
176    ; CHECK: [[LD2Twov2d:%[0-9]+]]:qq = LD2Twov2d %ptr :: (load (<2 x p0>))
177    ; CHECK: %dst1:fpr128 = COPY [[LD2Twov2d]].qsub0
178    ; CHECK: %dst2:fpr128 = COPY [[LD2Twov2d]].qsub1
179    ; CHECK: $q0 = COPY %dst1
180    ; CHECK: $q1 = COPY %dst2
181    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1
182    %ptr:gpr(p0) = COPY $x0
183    %dst1:fpr(<2 x p0>), %dst2:fpr(<2 x p0>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x p0>))
184    $q0 = COPY %dst1(<2 x p0>)
185    $q1 = COPY %dst2(<2 x p0>)
186    RET_ReallyLR implicit $q0, implicit $q1
187...
188---
189name:            LD1Twov1d_s64
190legalized:       true
191regBankSelected: true
192tracksRegLiveness: true
193body:             |
194  bb.0:
195    liveins: $x0, $x1, $x2
196    ; CHECK-LABEL: name: LD1Twov1d_s64
197    ; CHECK: liveins: $x0, $x1, $x2
198    ; CHECK: %ptr:gpr64sp = COPY $x0
199    ; CHECK: [[LD1Twov1d:%[0-9]+]]:dd = LD1Twov1d %ptr :: (load (s64))
200    ; CHECK: %dst1:fpr64 = COPY [[LD1Twov1d]].dsub0
201    ; CHECK: %dst2:fpr64 = COPY [[LD1Twov1d]].dsub1
202    ; CHECK: $d0 = COPY %dst1
203    ; CHECK: $d1 = COPY %dst2
204    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1
205    %ptr:gpr(p0) = COPY $x0
206    %dst1:fpr(s64), %dst2:fpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (s64))
207    $d0 = COPY %dst1(s64)
208    $d1 = COPY %dst2(s64)
209    RET_ReallyLR implicit $d0, implicit $d1
210...
211---
212name:            LD1Twov1d_p0
213legalized:       true
214regBankSelected: true
215tracksRegLiveness: true
216body:             |
217  bb.0:
218    liveins: $x0, $x1, $x2
219    ; CHECK-LABEL: name: LD1Twov1d_p0
220    ; CHECK: liveins: $x0, $x1, $x2
221    ; CHECK: %ptr:gpr64sp = COPY $x0
222    ; CHECK: [[LD1Twov1d:%[0-9]+]]:dd = LD1Twov1d %ptr :: (load (p0))
223    ; CHECK: %dst1:fpr64 = COPY [[LD1Twov1d]].dsub0
224    ; CHECK: %dst2:fpr64 = COPY [[LD1Twov1d]].dsub1
225    ; CHECK: $d0 = COPY %dst1
226    ; CHECK: $d1 = COPY %dst2
227    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1
228    %ptr:gpr(p0) = COPY $x0
229    %dst1:fpr(p0), %dst2:fpr(p0) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (p0))
230    $d0 = COPY %dst1(p0)
231    $d1 = COPY %dst2(p0)
232    RET_ReallyLR implicit $d0, implicit $d1
233