1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3...
4---
5name:            LD4Fourv8b
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $x0, $x1, $x2
12    ; CHECK-LABEL: name: LD4Fourv8b
13    ; CHECK: liveins: $x0, $x1, $x2
14    ; CHECK: %ptr:gpr64sp = COPY $x0
15    ; CHECK: [[LD4Fourv8b:%[0-9]+]]:dddd = LD4Fourv8b %ptr :: (load (<8 x s64>))
16    ; CHECK: %dst1:fpr64 = COPY [[LD4Fourv8b]].dsub0
17    ; CHECK: %dst2:fpr64 = COPY [[LD4Fourv8b]].dsub1
18    ; CHECK: %dst3:fpr64 = COPY [[LD4Fourv8b]].dsub2
19    ; CHECK: %dst4:fpr64 = COPY [[LD4Fourv8b]].dsub3
20    ; CHECK: $d0 = COPY %dst1
21    ; CHECK: $d1 = COPY %dst2
22    ; CHECK: $d2 = COPY %dst3
23    ; CHECK: $d3 = COPY %dst4
24    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
25    %ptr:gpr(p0) = COPY $x0
26    %dst1:fpr(<8 x s8>), %dst2:fpr(<8 x s8>), %dst3:fpr(<8 x s8>), %dst4:fpr(<8 x s8>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<8 x s64>))
27    $d0 = COPY %dst1(<8 x s8>)
28    $d1 = COPY %dst2(<8 x s8>)
29    $d2 = COPY %dst3(<8 x s8>)
30    $d3 = COPY %dst4(<8 x s8>)
31    RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
32...
33---
34name:            LD4Fourv16b
35legalized:       true
36regBankSelected: true
37tracksRegLiveness: true
38body:             |
39  bb.0:
40    liveins: $x0, $x1, $x2
41    ; CHECK-LABEL: name: LD4Fourv16b
42    ; CHECK: liveins: $x0, $x1, $x2
43    ; CHECK: %ptr:gpr64sp = COPY $x0
44    ; CHECK: [[LD4Fourv16b:%[0-9]+]]:qqqq = LD4Fourv16b %ptr :: (load (<16 x s64>))
45    ; CHECK: %dst1:fpr128 = COPY [[LD4Fourv16b]].qsub0
46    ; CHECK: %dst2:fpr128 = COPY [[LD4Fourv16b]].qsub1
47    ; CHECK: %dst3:fpr128 = COPY [[LD4Fourv16b]].qsub2
48    ; CHECK: %dst4:fpr128 = COPY [[LD4Fourv16b]].qsub3
49    ; CHECK: $q0 = COPY %dst1
50    ; CHECK: $q1 = COPY %dst2
51    ; CHECK: $q2 = COPY %dst3
52    ; CHECK: $q3 = COPY %dst4
53    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
54    %ptr:gpr(p0) = COPY $x0
55    %dst1:fpr(<16 x s8>), %dst2:fpr(<16 x s8>), %dst3:fpr(<16 x s8>), %dst4:fpr(<16 x s8>)  = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<16 x s64>))
56    $q0 = COPY %dst1(<16 x s8>)
57    $q1 = COPY %dst2(<16 x s8>)
58    $q2 = COPY %dst3(<16 x s8>)
59    $q3 = COPY %dst4(<16 x s8>)
60    RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
61...
62---
63name:            LD4Fourv4h
64legalized:       true
65regBankSelected: true
66tracksRegLiveness: true
67body:             |
68  bb.0:
69    liveins: $x0
70    ; CHECK-LABEL: name: LD4Fourv4h
71    ; CHECK: liveins: $x0
72    ; CHECK: %ptr:gpr64sp = COPY $x0
73    ; CHECK: [[LD4Fourv4h:%[0-9]+]]:dddd = LD4Fourv4h %ptr :: (load (<4 x s64>))
74    ; CHECK: %dst1:fpr64 = COPY [[LD4Fourv4h]].dsub0
75    ; CHECK: %dst2:fpr64 = COPY [[LD4Fourv4h]].dsub1
76    ; CHECK: %dst3:fpr64 = COPY [[LD4Fourv4h]].dsub2
77    ; CHECK: %dst4:fpr64 = COPY [[LD4Fourv4h]].dsub3
78    ; CHECK: $d0 = COPY %dst1
79    ; CHECK: $d1 = COPY %dst2
80    ; CHECK: $d2 = COPY %dst3
81    ; CHECK: $d3 = COPY %dst4
82    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
83    %ptr:gpr(p0) = COPY $x0
84    %dst1:fpr(<4 x s16>), %dst2:fpr(<4 x s16>), %dst3:fpr(<4 x s16>), %dst4:fpr(<4 x s16>)  = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<4 x s64>))
85    $d0 = COPY %dst1(<4 x s16>)
86    $d1 = COPY %dst2(<4 x s16>)
87    $d2 = COPY %dst3(<4 x s16>)
88    $d3 = COPY %dst4(<4 x s16>)
89    RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
90...
91---
92name:            LD4Fourv8h
93legalized:       true
94regBankSelected: true
95tracksRegLiveness: true
96body:             |
97  bb.0:
98    liveins: $x0, $x1, $x2
99    ; CHECK-LABEL: name: LD4Fourv8h
100    ; CHECK: liveins: $x0, $x1, $x2
101    ; CHECK: %ptr:gpr64sp = COPY $x0
102    ; CHECK: [[LD4Fourv8h:%[0-9]+]]:qqqq = LD4Fourv8h %ptr :: (load (<8 x s64>))
103    ; CHECK: %dst1:fpr128 = COPY [[LD4Fourv8h]].qsub0
104    ; CHECK: %dst2:fpr128 = COPY [[LD4Fourv8h]].qsub1
105    ; CHECK: %dst3:fpr128 = COPY [[LD4Fourv8h]].qsub2
106    ; CHECK: %dst4:fpr128 = COPY [[LD4Fourv8h]].qsub3
107    ; CHECK: $q0 = COPY %dst1
108    ; CHECK: $q1 = COPY %dst2
109    ; CHECK: $q2 = COPY %dst3
110    ; CHECK: $q3 = COPY %dst4
111    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
112    %ptr:gpr(p0) = COPY $x0
113    %dst1:fpr(<8 x s16>), %dst2:fpr(<8 x s16>), %dst3:fpr(<8 x s16>), %dst4:fpr(<8 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<8 x s64>))
114    $q0 = COPY %dst1(<8 x s16>)
115    $q1 = COPY %dst2(<8 x s16>)
116    $q2 = COPY %dst3(<8 x s16>)
117    $q3 = COPY %dst4(<8 x s16>)
118    RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
119...
120---
121name:            LD4Fourv2s
122legalized:       true
123regBankSelected: true
124tracksRegLiveness: true
125body:             |
126  bb.0:
127    liveins: $x0, $x1, $x2
128    ; CHECK-LABEL: name: LD4Fourv2s
129    ; CHECK: liveins: $x0, $x1, $x2
130    ; CHECK: %ptr:gpr64sp = COPY $x0
131    ; CHECK: [[LD4Fourv2s:%[0-9]+]]:dddd = LD4Fourv2s %ptr :: (load (<2 x s64>))
132    ; CHECK: %dst1:fpr64 = COPY [[LD4Fourv2s]].dsub0
133    ; CHECK: %dst2:fpr64 = COPY [[LD4Fourv2s]].dsub1
134    ; CHECK: %dst3:fpr64 = COPY [[LD4Fourv2s]].dsub2
135    ; CHECK: %dst4:fpr64 = COPY [[LD4Fourv2s]].dsub3
136    ; CHECK: $d0 = COPY %dst1
137    ; CHECK: $d1 = COPY %dst2
138    ; CHECK: $d2 = COPY %dst3
139    ; CHECK: $d3 = COPY %dst4
140    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
141    %ptr:gpr(p0) = COPY $x0
142    %dst1:fpr(<2 x s32>), %dst2:fpr(<2 x s32>), %dst3:fpr(<2 x s32>), %dst4:fpr(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x s64>))
143    $d0 = COPY %dst1(<2 x s32>)
144    $d1 = COPY %dst2(<2 x s32>)
145    $d2 = COPY %dst3(<2 x s32>)
146    $d3 = COPY %dst4(<2 x s32>)
147    RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
148...
149---
150name:            LD4Fourv4s
151legalized:       true
152regBankSelected: true
153tracksRegLiveness: true
154body:             |
155  bb.0:
156    liveins: $x0, $x1, $x2
157    ; CHECK-LABEL: name: LD4Fourv4s
158    ; CHECK: liveins: $x0, $x1, $x2
159    ; CHECK: %ptr:gpr64sp = COPY $x0
160    ; CHECK: [[LD4Fourv4s:%[0-9]+]]:qqqq = LD4Fourv4s %ptr :: (load (<4 x s64>))
161    ; CHECK: %dst1:fpr128 = COPY [[LD4Fourv4s]].qsub0
162    ; CHECK: %dst2:fpr128 = COPY [[LD4Fourv4s]].qsub1
163    ; CHECK: %dst3:fpr128 = COPY [[LD4Fourv4s]].qsub2
164    ; CHECK: %dst4:fpr128 = COPY [[LD4Fourv4s]].qsub3
165    ; CHECK: $q0 = COPY %dst1
166    ; CHECK: $q1 = COPY %dst2
167    ; CHECK: $q2 = COPY %dst3
168    ; CHECK: $q3 = COPY %dst4
169    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
170    %ptr:gpr(p0) = COPY $x0
171    %dst1:fpr(<4 x s32>), %dst2:fpr(<4 x s32>), %dst3:fpr(<4 x s32>), %dst4:fpr(<4 x s32>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<4 x s64>))
172    $q0 = COPY %dst1(<4 x s32>)
173    $q1 = COPY %dst2(<4 x s32>)
174    $q2 = COPY %dst3(<4 x s32>)
175    $q3 = COPY %dst4(<4 x s32>)
176    RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
177...
178---
179name:            LD4Fourv2d_v2s64
180legalized:       true
181regBankSelected: true
182tracksRegLiveness: true
183body:             |
184  bb.0:
185    liveins: $x0, $x1, $x2
186    ; CHECK-LABEL: name: LD4Fourv2d_v2s64
187    ; CHECK: liveins: $x0, $x1, $x2
188    ; CHECK: %ptr:gpr64sp = COPY $x0
189    ; CHECK: [[LD4Fourv2d:%[0-9]+]]:qqqq = LD4Fourv2d %ptr :: (load (<2 x s64>))
190    ; CHECK: %dst1:fpr128 = COPY [[LD4Fourv2d]].qsub0
191    ; CHECK: %dst2:fpr128 = COPY [[LD4Fourv2d]].qsub1
192    ; CHECK: %dst3:fpr128 = COPY [[LD4Fourv2d]].qsub2
193    ; CHECK: %dst4:fpr128 = COPY [[LD4Fourv2d]].qsub3
194    ; CHECK: $q0 = COPY %dst1
195    ; CHECK: $q1 = COPY %dst2
196    ; CHECK: $q2 = COPY %dst3
197    ; CHECK: $q3 = COPY %dst4
198    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
199    %ptr:gpr(p0) = COPY $x0
200    %dst1:fpr(<2 x s64>), %dst2:fpr(<2 x s64>), %dst3:fpr(<2 x s64>), %dst4:fpr(<2 x s64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x s64>))
201    $q0 = COPY %dst1(<2 x s64>)
202    $q1 = COPY %dst2(<2 x s64>)
203    $q2 = COPY %dst3(<2 x s64>)
204    $q3 = COPY %dst4(<2 x s64>)
205    RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
206...
207---
208name:            LD4Fourv2d_v2p0
209legalized:       true
210regBankSelected: true
211tracksRegLiveness: true
212body:             |
213  bb.0:
214    liveins: $x0, $x1, $x2
215    ; CHECK-LABEL: name: LD4Fourv2d_v2p0
216    ; CHECK: liveins: $x0, $x1, $x2
217    ; CHECK: %ptr:gpr64sp = COPY $x0
218    ; CHECK: [[LD4Fourv2d:%[0-9]+]]:qqqq = LD4Fourv2d %ptr :: (load (<2 x p0>))
219    ; CHECK: %dst1:fpr128 = COPY [[LD4Fourv2d]].qsub0
220    ; CHECK: %dst2:fpr128 = COPY [[LD4Fourv2d]].qsub1
221    ; CHECK: %dst3:fpr128 = COPY [[LD4Fourv2d]].qsub2
222    ; CHECK: %dst4:fpr128 = COPY [[LD4Fourv2d]].qsub3
223    ; CHECK: $q0 = COPY %dst1
224    ; CHECK: $q1 = COPY %dst2
225    ; CHECK: $q2 = COPY %dst3
226    ; CHECK: $q3 = COPY %dst4
227    ; CHECK: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
228    %ptr:gpr(p0) = COPY $x0
229    %dst1:fpr(<2 x p0>), %dst2:fpr(<2 x p0>), %dst3:fpr(<2 x p0>), %dst4:fpr(<2 x p0>)  = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x p0>))
230    $q0 = COPY %dst1(<2 x p0>)
231    $q1 = COPY %dst2(<2 x p0>)
232    $q2 = COPY %dst3(<2 x p0>)
233    $q3 = COPY %dst4(<2 x p0>)
234    RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
235...
236---
237name:            LD1Fourv1d_s64
238legalized:       true
239regBankSelected: true
240tracksRegLiveness: true
241body:             |
242  bb.0:
243    liveins: $x0, $x1, $x2
244    ; CHECK-LABEL: name: LD1Fourv1d_s64
245    ; CHECK: liveins: $x0, $x1, $x2
246    ; CHECK: %ptr:gpr64sp = COPY $x0
247    ; CHECK: [[LD1Fourv1d:%[0-9]+]]:dddd = LD1Fourv1d %ptr :: (load (s64))
248    ; CHECK: %dst1:fpr64 = COPY [[LD1Fourv1d]].dsub0
249    ; CHECK: %dst2:fpr64 = COPY [[LD1Fourv1d]].dsub1
250    ; CHECK: %dst3:fpr64 = COPY [[LD1Fourv1d]].dsub2
251    ; CHECK: %dst4:fpr64 = COPY [[LD1Fourv1d]].dsub3
252    ; CHECK: $d0 = COPY %dst1
253    ; CHECK: $d1 = COPY %dst2
254    ; CHECK: $d2 = COPY %dst3
255    ; CHECK: $d3 = COPY %dst4
256    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
257    %ptr:gpr(p0) = COPY $x0
258    %dst1:fpr(s64), %dst2:fpr(s64), %dst3:fpr(s64), %dst4:fpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (s64))
259    $d0 = COPY %dst1(s64)
260    $d1 = COPY %dst2(s64)
261    $d2 = COPY %dst3(s64)
262    $d3 = COPY %dst4(s64)
263    RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
264...
265---
266name:            LD1Fourv1d_p0
267legalized:       true
268regBankSelected: true
269tracksRegLiveness: true
270body:             |
271  bb.0:
272    liveins: $x0, $x1, $x2
273    ; CHECK-LABEL: name: LD1Fourv1d_p0
274    ; CHECK: liveins: $x0, $x1, $x2
275    ; CHECK: %ptr:gpr64sp = COPY $x0
276    ; CHECK: [[LD1Fourv1d:%[0-9]+]]:dddd = LD1Fourv1d %ptr :: (load (p0))
277    ; CHECK: %dst1:fpr64 = COPY [[LD1Fourv1d]].dsub0
278    ; CHECK: %dst2:fpr64 = COPY [[LD1Fourv1d]].dsub1
279    ; CHECK: %dst3:fpr64 = COPY [[LD1Fourv1d]].dsub2
280    ; CHECK: %dst4:fpr64 = COPY [[LD1Fourv1d]].dsub3
281    ; CHECK: $d0 = COPY %dst1
282    ; CHECK: $d1 = COPY %dst2
283    ; CHECK: $d2 = COPY %dst3
284    ; CHECK: $d3 = COPY %dst4
285    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
286    %ptr:gpr(p0) = COPY $x0
287    %dst1:fpr(p0), %dst2:fpr(p0), %dst3:fpr(p0), %dst4:fpr(p0) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (p0))
288    $d0 = COPY %dst1(p0)
289    $d1 = COPY %dst2(p0)
290    $d2 = COPY %dst3(p0)
291    $d3 = COPY %dst4(p0)
292    RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
293