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Searched refs:createReg (Results 1 – 25 of 92) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1346 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR64RegisterClass()
1356 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRMM16RegisterClass()
1366 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRMM16ZeroRegisterClass()
1376 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRMM16MovePRegisterClass()
1386 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
1412 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFGR64RegisterClass()
1423 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFGR32RegisterClass()
1433 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCCRRegisterClass()
1443 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFCCRegisterClass()
1454 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFGRCCRegisterClass()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp74 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR8RegisterClass()
85 Inst.addOperand(MCOperand::createReg(Register)); in DecodeLD8RegisterClass()
333 Inst.addOperand(MCOperand::createReg(RegBase)); in decodeLoadStore()
334 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
344 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
345 Inst.addOperand(MCOperand::createReg(RegBase)); in decodeLoadStore()
359 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
360 Inst.addOperand(MCOperand::createReg(RegBase)); in decodeLoadStore()
361 Inst.addOperand(MCOperand::createReg(RegBase)); in decodeLoadStore()
363 Inst.addOperand(MCOperand::createReg(RegBase)); in decodeLoadStore()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp114 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRRegisterClass()
124 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodeFPR32RegisterClass()
134 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodesFPR32RegisterClass()
144 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodesFPR64RegisterClass()
186 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodesGPRRegisterClass()
196 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodemGPRRegisterClass()
208 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRSPRegisterClass()
393 MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14)); in handleCROperand()
394 MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14)); in handleCROperand()
455 MI.insert(MI.begin(), MCOperand::createReg(CSKY::C)); in handleCROperand()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
255 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
267 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
284 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
289 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
306 Inst.addOperand(MCOperand::createReg(RRegs[Base])); in decodeMemRIHashOperands()
322 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIX16Operands()
351 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRI34Operands()
367 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeSPE8Operands()
383 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeSPE4Operands()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVMCInstLower.cpp36 MCOp = MCOperand::createReg(FuncReg); in lower()
40 MCOp = MCOperand::createReg(MAI->getOrCreateMBBRegister(*MO.getMBB())); in lower()
44 MCOp = MCOperand::createReg(NewReg.isValid() ? NewReg : MO.getReg()); in lower()
50 MCOp = MCOperand::createReg(Reg); in lower()
H A DSPIRVAsmPrinter.cpp140 LabelInst.addOperand(MCOperand::createReg(MAI->getOrCreateMBBRegister(MBB))); in emitOpLabel()
270 Inst.addOperand(MCOperand::createReg(Reg)); in outputOpExtInstImports()
314 TmpInst.addOperand(MCOperand::createReg(Reg)); in outputEntryPoints()
372 Inst.addOperand(MCOperand::createReg(FuncReg)); in addOpsFromMDNode()
382 Inst.addOperand(MCOperand::createReg(Reg)); in outputExecutionModeFromMDNode()
416 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode()
452 Inst.addOperand(MCOperand::createReg(Reg)); in outputAnnotations()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp72 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
83 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass()
94 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
105 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
116 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
127 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
158 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
169 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRPF64RegisterClass()
180 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRRegisterClass()
200 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRM2RegisterClass()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/Disassembler/
H A DLoongArchDisassembler.cpp63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); in DecodeGPRRegisterClass()
72 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo)); in DecodeFPR32RegisterClass()
81 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo)); in DecodeFPR64RegisterClass()
90 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo)); in DecodeCFRRegisterClass()
99 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo)); in DecodeFCSRRegisterClass()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp87 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
316 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
327 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
339 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
351 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len4Operand()
363 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
375 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDRAddr12Operand()
377 Inst.addOperand(MCOperand::createReg(Regs[Length])); in decodeBDRAddr12Operand()
387 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDVAddr12Operand()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp40 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
46 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
188 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
219 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
220 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
237 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
238 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
239 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
257 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRIII()
258 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRIII()
1307 Inst.addOperand(MCOperand::createReg(GPReg)); in emitDirectiveCpreturn()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp1800 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
1828 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
1853 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
2104 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
2105 indexReg = MCOperand::createReg(X86::SI); in translateRMMemory()
2108 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
2109 indexReg = MCOperand::createReg(X86::DI); in translateRMMemory()
2112 baseReg = MCOperand::createReg(X86::BP); in translateRMMemory()
2113 indexReg = MCOperand::createReg(X86::SI); in translateRMMemory()
2116 baseReg = MCOperand::createReg(X86::BP); in translateRMMemory()
[all …]
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp2433 Inst.addOperand(MCOperand::createReg(SrcReg)); in createSaveToStack()
2459 Inst.addOperand(MCOperand::createReg(DstReg)); in createLoad()
2475 Inst.addOperand(MCOperand::createReg(Dest)); in createLoadImmediate()
3095 Inst.addOperand(MCOperand::createReg(Reg)); in createPushRegister()
3121 Inst.addOperand(MCOperand::createReg(Reg)); in createPopRegister()
3144 Inst.addOperand(MCOperand::createReg(Reg)); in createAddRegImm()
3145 Inst.addOperand(MCOperand::createReg(Reg)); in createAddRegImm()
3167 Inst.addOperand(MCOperand::createReg(Reg)); in createClearRegWithNoEFlagsUpdate()
3174 Inst.addOperand(MCOperand::createReg(Reg)); in createX86SaveOVFlagToRegister()
3711 Inst.addOperand(MCOperand::createReg(Reg)); in createMove()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h537 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
545 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
554 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR16orGR32orGR64Operands()
588 Inst.addOperand(MCOperand::createReg(Reg)); in addMaskPairOperands()
594 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
598 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
600 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
614 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands()
615 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands()
620 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addDstIdxOperands()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp186 MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); in lowerGETGOTAndEmitMCInsts()
203 MCOperand RegGOT = MCOperand::createReg(VE::SX15); // GOT in lowerGETGOTAndEmitMCInsts()
204 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETGOTAndEmitMCInsts()
225 MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); in lowerGETFunPLTAndEmitMCInsts()
252 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETFunPLTAndEmitMCInsts()
293 MCOperand RegLR = MCOperand::createReg(VE::SX10); // LR in lowerGETTLSAddrAndEmitMCInsts()
294 MCOperand RegS0 = MCOperand::createReg(VE::SX0); // S0 in lowerGETTLSAddrAndEmitMCInsts()
295 MCOperand RegS12 = MCOperand::createReg(VE::SX12); // S12 in lowerGETTLSAddrAndEmitMCInsts()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp1116 MI.addOperand(MCOperand::createReg(DefRegister)); in LowerFAULTING_OP()
1144 MOVI.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1153 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1158 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1163 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1239 MovZ.addOperand(MCOperand::createReg(DestReg)); in emitInstruction()
1246 MovK.addOperand(MCOperand::createReg(DestReg)); in emitInstruction()
1247 MovK.addOperand(MCOperand::createReg(DestReg)); in emitInstruction()
1360 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in emitInstruction()
1372 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); in emitInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2495 Inst.addOperand(MCOperand::createReg(0)); in addVPTPredNOperands()
2586 Inst.addOperand(MCOperand::createReg(Reg)); in addRegListOperands()
2593 Inst.addOperand(MCOperand::createReg(Reg)); in addRegListWithAPSROperands()
2991 Inst.addOperand(MCOperand::createReg(0)); in addAM2OffsetImmOperands()
3002 Inst.addOperand(MCOperand::createReg(0)); in addAddrMode3Operands()
3051 Inst.addOperand(MCOperand::createReg(0)); in addAM3OffsetOperands()
8721 TmpInst.addOperand(MCOperand::createReg(0)); in processInstruction()
10060 TmpInst.addOperand(MCOperand::createReg( in processInstruction()
10067 TmpInst.addOperand(MCOperand::createReg( in processInstruction()
10113 TmpInst.addOperand(MCOperand::createReg( in processInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp100 MCOp = MCOperand::createReg(MO.getReg()); in lowerRISCVMachineOperandToMCOperand()
195 MCOp = MCOperand::createReg(Reg); in lowerRISCVVMachineInstrToMCInst()
208 OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister)); in lowerRISCVVMachineInstrToMCInst()
244 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
250 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
180 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
195 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
206 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp402 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass()
422 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass()
434 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass()
446 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass()
458 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass()
471 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64commonRegisterClass()
483 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass()
498 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64x8ClassRegisterClass()
509 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64spRegisterClass()
523 Inst.addOperand(MCOperand::createReg(Register)); in DecodeMatrixIndexGPR32_12_15RegisterClass()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp108 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
123 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
134 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeMemoryOpValue()
215 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DJTFootprintReduction.cpp157 MCOperand RegOp = MCOperand::createReg(Reg); in tryOptimizeNonPIC()
161 MCOperand::createReg(Index), Offset, RegOp); in tryOptimizeNonPIC()
195 MCOperand RegOp = MCOperand::createReg(BaseReg); in tryOptimizePIC()
198 BC.MIB->createIJmp32Frag(NewFrag, MCOperand::createReg(0), in tryOptimizePIC()
200 MCOperand::createReg(Index), JumpTableRef, RegOp); in tryOptimizePIC()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp151 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass()
161 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass()
171 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass()
181 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass()
194 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass()
204 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCPRegsRegisterClass()
213 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
222 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass()
231 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass()
247 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass()
[all …]
/llvm-project-15.0.7/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp964 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
973 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
974 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
983 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
984 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
993 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
1023 Inst.addOperand(MCOperand::createReg(Reg)); in createShortJmp()
1113 Inst.addOperand(MCOperand::createReg(AArch64::LR)); in createReturn()
1124 Insts[0].addOperand(MCOperand::createReg(RegName)); in materializeAddress()
1130 Insts[1].addOperand(MCOperand::createReg(RegName)); in materializeAddress()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp423 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
433 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
443 Inst.addOperand(MCOperand::createReg(XRegs[getG8pReg()])); in addRegG8pRCOperands()
462 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
467 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
472 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); in addRegVFRCOperands()
477 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
482 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
497 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegSPE4RCOperands()
502 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()])); in addRegSPERCOperands()
[all …]

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