| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm() 158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm() 165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm() 173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm() 175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm() 266 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedStore() 305 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI)) in select() 378 if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI)) in select() 386 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select() 397 if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI)) in select() [all …]
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| H A D | MipsLegalizerInfo.cpp | 515 return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI); in legalizeIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 584 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) in insertComparison() 592 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI)) in insertComparison() 603 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI)) in insertComparison() 709 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal() 716 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal() 764 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal() 781 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) in selectSelect() 797 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI)) in selectSelect() 810 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectShift() 1129 if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI)) in select() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1825 constrainSelectedInstRegOperands(*Shl, TII, TRI, RBI); in selectVectorSHL() 1882 constrainSelectedInstRegOperands(*Neg, TII, TRI, RBI); in selectVectorAshrLshr() 1884 constrainSelectedInstRegOperands(*SShl, TII, TRI, RBI); in selectVectorAshrLshr() 1908 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectVaStartDarwin() 1916 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectVaStartDarwin() 1932 constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI); in materializeLargeCMVal() 2618 constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select() 3320 constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select() 3931 constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI); in selectVectorICmp() 4036 constrainSelectedInstRegOperands(BFM, TII, TRI, RBI); in selectMergeValues() [all …]
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| H A D | AArch64LegalizerInfo.cpp | 1113 constrainSelectedInstRegOperands(*NewI, *ST->getInstrInfo(), in legalizeLoadStore() 1380 constrainSelectedInstRegOperands(*CAS, *ST->getInstrInfo(), in legalizeAtomicCmpxchg128()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 550 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectLoadStoreOp() 587 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectFrameIndexOrGep() 633 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectGlobalValue() 833 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI); in selectZext() 938 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); in selectCmp() 939 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI); in selectCmp() 1006 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI); in selectFCmp() 1007 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI); in selectFCmp() 1008 constrainSelectedInstRegOperands(Set3, TII, TRI, RBI); in selectFCmp() 1030 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); in selectFCmp() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 301 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_AND_OR_XOR() 334 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_ADD_SUB() 347 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); in selectG_ADD_SUB() 387 if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI)) in selectG_ADD_SUB() 424 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_UADDO_USUBO_UADDE_USUBE() 476 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_AMDGPU_MAD_64_32() 706 return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); in selectG_BUILD_VECTOR_TRUNC() 808 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_SBFX_UBFX() 910 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectWritelane() 951 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDivScale() [all …]
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| H A D | AMDGPURegisterBankInfo.cpp | 1551 if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this)) in applyMappingBFE()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVGlobalRegistry.cpp | 171 constrainSelectedInstRegOperands(*MIB, *ST.getInstrInfo(), in getOrCreateConstInt() 214 constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(), in buildConstantInt() 289 constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(), in getOrCreateConsIntVector() 339 constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(), in buildGlobalVariable() 809 constrainSelectedInstRegOperands(*MIB, *ST.getInstrInfo(), in getOrCreateUndef()
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| H A D | SPIRVInstructionSelector.cpp | 895 constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in buildI32Constant()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 138 bool constrainSelectedInstRegOperands(MachineInstr &I,
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| H A D | InstructionSelectorImpl.h | 1102 constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI, in executeMatchTable()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 323 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in constrainAllUses()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 150 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, in constrainSelectedInstRegOperands() function in llvm
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