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Searched refs:constrainRegClass (Results 1 – 25 of 39) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp366 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
369 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass); in AssignSlot()
372 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass); in AssignSlot()
375 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass); in AssignSlot()
H A DSILowerI1Copies.cpp483 MRI->constrainRegClass(Reg, &AMDGPU::SReg_1_XEXECRegClass); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp67 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() function
83 MachineRegisterInfo::constrainRegClass(Register Reg, in constrainRegClass() function in MachineRegisterInfo
86 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
107 if (!::constrainRegClass( in constrainRegAttrs()
H A DOptimizePHIs.cpp180 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
H A DUnreachableBlockElim.cpp176 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in runOnMachineFunction()
H A DMachineLoopUtils.cpp67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg())); in PeelSingleBlockLoop()
H A DTargetInstrInfo.cpp849 MRI.constrainRegClass(RegA, RC); in reassociateOps()
851 MRI.constrainRegClass(RegB, RC); in reassociateOps()
853 MRI.constrainRegClass(RegX, RC); in reassociateOps()
855 MRI.constrainRegClass(RegY, RC); in reassociateOps()
857 MRI.constrainRegClass(RegC, RC); in reassociateOps()
H A DTailDuplicator.cpp251 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in tailDuplicateAndUpdate()
428 ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC); in duplicateInstruction()
H A DModuloSchedule.cpp1167 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
1222 MRI.constrainRegClass(MI.getOperand(1).getReg(), in EliminateDeadPhis()
1475 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.value())); in phi()
1488 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
H A DRegisterBankInfo.cpp135 return MRI.constrainRegClass(Reg, &RC); in constrainGenericRegister()
H A DTwoAddressInstructionPass.cpp1435 MRI->constrainRegClass(DstReg, RC); in collectTiedOperands()
1558 MRI->constrainRegClass(RegA, RC); in processTiedPairs()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp104 if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) { in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp453 MRI->constrainRegClass(SrcReg, FirstInstrOperandRC); in splitTwoPartImm()
454 MRI->constrainRegClass(NewTmpReg, SecondInstrOperandRC); in splitTwoPartImm()
456 MRI->constrainRegClass(NewDstReg, MRI->getRegClass(DstReg)); in splitTwoPartImm()
H A DAArch64ConditionalCompares.cpp643 MRI->constrainRegClass(HeadCond[2].getReg(), in convert()
690 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert()
693 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), in convert()
H A DAArch64InstrInfo.cpp776 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
777 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
5483 MRI.constrainRegClass(ResultReg, RC); in genFusedMultiply()
5485 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
5487 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply()
5489 MRI.constrainRegClass(SrcReg2, RC); in genFusedMultiply()
5535 MRI.constrainRegClass(DupSrcReg, RC); in genIndexedMultiply()
5662 MRI.constrainRegClass(ResultReg, RC); in genMaddR()
5664 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
5666 MRI.constrainRegClass(SrcReg1, RC); in genMaddR()
[all …]
H A DAArch64RegisterInfo.cpp623 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp395 MRI->constrainRegClass(StartReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
396 MRI->constrainRegClass(PhiReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
397 MRI->constrainRegClass(DecReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
530 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
H A DThumb2InstrInfo.cpp193 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
234 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass); in loadRegFromStackSlot()
726 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
H A DARMLoadStoreOptimizer.cpp2435 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2436 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
2737 MRI.constrainRegClass(NewBaseReg, TRC); in AdjustBaseAndOffset()
2794 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore()
2797 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
H A DA15SDOptimizer.cpp635 MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg())); in runOnInstruction()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp237 if (!MRI.constrainRegClass(KilledProdReg, in processBlock()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSExtWRemoval.cpp470 if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg))) in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp328 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
458 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); in ConstrainForSubReg()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp507 if (!MRI.constrainRegClass(DestReg, PreviousClass)) in optimizeSelect()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h702 const TargetRegisterClass *constrainRegClass(Register Reg,

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