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/llvm-project-15.0.7/lldb/third_party/Python/module/pexpect-4.6/pexpect/
H A Dscreen.py60 def constrain (n, min, max): function
158 rs = constrain (rs, 1, self.rows)
159 re = constrain (re, 1, self.rows)
160 cs = constrain (cs, 1, self.cols)
161 ce = constrain (ce, 1, self.cols)
203 r = constrain (r, 1, self.rows)
204 c = constrain (c, 1, self.cols)
229 r = constrain (r, 1, self.rows)
230 c = constrain (c, 1, self.cols)
244 r = constrain (r, 1, self.rows)
[all …]
/llvm-project-15.0.7/clang/include/clang/Analysis/
H A DCloneDetection.h186 C.constrain(CloneGroups); in constrainClones()
256 void constrain(std::vector<CloneDetector::CloneGroup> &Sequences);
267 void constrain(std::vector<CloneDetector::CloneGroup> &Sequences);
289 void constrain(std::vector<CloneDetector::CloneGroup> &CloneGroups) { in constrain() function
309 void constrain(std::vector<CloneDetector::CloneGroup> &CloneGroups) { in constrain() function
319 void constrain(std::vector<CloneDetector::CloneGroup> &Result);
334 void constrain(std::vector<CloneDetector::CloneGroup> &CloneGroups) { in constrain() function
433 void constrain(std::vector<CloneDetector::CloneGroup> &CloneGroups);
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Darm-select-copy_to_regclass-of-fptosi.mir5 # Test that we constrain register classes of temporary virtual registers
9 # COPY_TO_REGCLASS doesn't constrain its source register class. It exposes the
10 # bug as we create a tmp reg for VTOSIZS' result and don't constrain its
/llvm-project-15.0.7/clang/lib/Analysis/
H A DCloneDetection.cpp126 void OnlyLargestCloneConstraint::constrain( in constrain() function in OnlyLargestCloneConstraint
350 void RecursiveCloneTypeIIHashConstraint::constrain( in constrain() function in RecursiveCloneTypeIIHashConstraint
410 void RecursiveCloneTypeIIVerifyConstraint::constrain( in constrain() function in RecursiveCloneTypeIIVerifyConstraint
464 void MatchingVariablePatternConstraint::constrain( in constrain() function in MatchingVariablePatternConstraint
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-xor.mir17 # Also check that we constrain the register class of the COPY to GPR32.
70 # Also check that we constrain the register class of the COPY to GPR32.
H A Dselect-intrinsic-aarch64-sdiv.mir12 # Also check that we constrain the register class of the COPY to GPR32.
H A Dselect-binop.mir5 # Also check that we constrain the register class of the COPY to GPR32.
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dselect-intrinsic-x86-flags-read-u32.mir5 # instruction. Also check that we constrain the register class of the COPY to
/llvm-project-15.0.7/clang/unittests/Analysis/
H A DCloneDetectionTest.cpp37 void constrain(std::vector<CloneDetector::CloneGroup> &CloneGroups) { in constrain() function in clang::analysis::__anon92d107290111::NoBarFunctionConstraint
/llvm-project-15.0.7/mlir/include/mlir/Dialect/PDL/IR/
H A DPDLOps.td103 Instances of this operation define, and partially constrain, attributes of a
104 given operation. A `pdl.attribute` may partially constrain the input by
175 may partially constrain an operand by specifying an expected value type
214 given operation. A `pdl.operands` may partially constrain a set of input
624 partially constrain, results types of a given entity. A `pdl.type` may
625 partially constrain the result by specifying a constant `Type`.
653 entity. A `pdl.types` may partially constrain the results by specifying
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Tensor/IR/
H A DTensorBase.td38 Thus, for the `tensor` dialect, we prefer for now to constrain the
/llvm-project-15.0.7/pstl/
H A DCMakeLists.txt23 set(PSTL_HIDE_FROM_ABI_PER_TU OFF CACHE BOOL "Whether to constrain ABI-unstable symbols to each tra…
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpr38539.ll60 …bitwidth adjusted to target 32-bit mode. This also shows that we didn't constrain the register cla…
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dswp-intreglow8.ll4 ; Test that we constrain the new register operands for instructions
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h240 bool constrain(const TypeSetByHwMode &VTS);
241 template <typename Predicate> bool constrain(Predicate P);
H A DCodeGenDAGPatterns.cpp150 bool TypeSetByHwMode::constrain(const TypeSetByHwMode &VTS) { in constrain() function in TypeSetByHwMode
176 bool TypeSetByHwMode::constrain(Predicate P) { in constrain() function in TypeSetByHwMode
381 bool Changed = Out.constrain(In); in MergeInTypeInfo()
412 return Out.constrain(isIntegerOrPtr); in EnforceInteger()
422 return Out.constrain(isFloatingPoint); in EnforceFloatingPoint()
432 return Out.constrain(isScalar); in EnforceScalar()
442 return Out.constrain(isVector); in EnforceVector()
/llvm-project-15.0.7/llvm/lib/Support/Windows/
H A DThreading.inc203 // If there's an affinity mask set, assume the user wants to constrain the
/llvm-project-15.0.7/libcxx/docs/Status/
H A DCxx2bIssues.csv29 "`3425 <https://wg21.link/LWG3425>`__","``condition_variable_any`` fails to constrain its Lock para…
133 …`const`` lvalue reference overload of ``get`` for ``subrange`` does not constrain ``I`` to be ``co…
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DGMIR.rst100 instructions. Register Banks are a means to constrain the register allocator to
/llvm-project-15.0.7/llvm/docs/
H A DFAQ.rst191 of leaving it in a local variable. If you really want to constrain the
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/
H A Ddyn-symbols-size-from-hash-table.test226 ## constrain the .dynsym section header to say there are only 3. This means that
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinst-select-xor.mir428 # The selector for the copy of the xor result may constrain the result
H A Dinst-select-or.mir427 # The selector for the copy of the or result may constrain the result
H A Dinst-select-and.mir427 # The selector for the copy of the and result may constrain the result
/llvm-project-15.0.7/mlir/docs/
H A DShapeInference.md245 an operation. Where these are sufficient to constrain the output shape (e.g.,

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