1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3--- 4# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32. 5# Also check that we constrain the register class of the COPY to GPR32. 6name: add_s32_gpr 7legalized: true 8regBankSelected: true 9 10registers: 11 - { id: 0, class: gpr } 12 - { id: 1, class: gpr } 13 - { id: 2, class: gpr } 14 15body: | 16 bb.0: 17 liveins: $w0, $w1 18 19 ; CHECK-LABEL: name: add_s32_gpr 20 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 21 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 22 ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]] 23 ; CHECK: $w0 = COPY [[ADDWrr]] 24 %0(s32) = COPY $w0 25 %1(s32) = COPY $w1 26 %2(s32) = G_ADD %0, %1 27 $w0 = COPY %2(s32) 28... 29 30--- 31# Same as add_s32_gpr, for 64-bit operations. 32name: add_s64_gpr 33legalized: true 34regBankSelected: true 35 36registers: 37 - { id: 0, class: gpr } 38 - { id: 1, class: gpr } 39 - { id: 2, class: gpr } 40 41body: | 42 bb.0: 43 liveins: $x0, $x1 44 45 ; CHECK-LABEL: name: add_s64_gpr 46 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 47 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 48 ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]] 49 ; CHECK: $x0 = COPY [[ADDXrr]] 50 %0(s64) = COPY $x0 51 %1(s64) = COPY $x1 52 %2(s64) = G_ADD %0, %1 53 $x0 = COPY %2(s64) 54... 55 56--- 57name: add_imm_s32_gpr 58legalized: true 59regBankSelected: true 60 61registers: 62 - { id: 0, class: gpr } 63 - { id: 1, class: gpr } 64 - { id: 2, class: gpr } 65 66body: | 67 bb.0: 68 liveins: $w0, $w1 69 70 ; CHECK-LABEL: name: add_imm_s32_gpr 71 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 72 ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 73 ; CHECK: $w0 = COPY [[ADDWri]] 74 %0(s32) = COPY $w0 75 %1(s32) = G_CONSTANT i32 1 76 %2(s32) = G_ADD %0, %1 77 $w0 = COPY %2(s32) 78... 79 80--- 81name: add_imm_s64_gpr 82legalized: true 83regBankSelected: true 84 85registers: 86 - { id: 0, class: gpr } 87 - { id: 1, class: gpr } 88 - { id: 2, class: gpr } 89 90body: | 91 bb.0: 92 liveins: $x0, $w1 93 94 ; CHECK-LABEL: name: add_imm_s64_gpr 95 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 96 ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0 97 ; CHECK: $x0 = COPY [[ADDXri]] 98 %0(s64) = COPY $x0 99 %1(s64) = G_CONSTANT i64 1 100 %2(s64) = G_ADD %0, %1 101 $x0 = COPY %2(s64) 102... 103 104--- 105name: add_neg_s32_gpr 106legalized: true 107regBankSelected: true 108 109registers: 110 - { id: 0, class: gpr } 111 - { id: 1, class: gpr } 112 - { id: 2, class: gpr } 113 114body: | 115 bb.0: 116 liveins: $w1, $w2 117 ; We should be able to turn the ADD into a SUB. 118 ; CHECK-LABEL: name: add_neg_s32_gpr 119 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w1 120 ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv 121 ; CHECK: $w2 = COPY [[SUBSWri]] 122 %0(s32) = COPY $w1 123 %1(s32) = G_CONSTANT i32 -1 124 %2(s32) = G_ADD %0, %1 125 $w2 = COPY %2(s32) 126... 127 128--- 129name: add_neg_s64_gpr 130legalized: true 131regBankSelected: true 132 133registers: 134 - { id: 0, class: gpr } 135 - { id: 1, class: gpr } 136 - { id: 2, class: gpr } 137 138body: | 139 bb.0: 140 liveins: $x0, $x1 141 ; We should be able to turn the ADD into a SUB. 142 ; CHECK-LABEL: name: add_neg_s64_gpr 143 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 144 ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 0, implicit-def $nzcv 145 ; CHECK: $x0 = COPY [[SUBSXri]] 146 %0(s64) = COPY $x0 147 %1(s64) = G_CONSTANT i64 -1 148 %2(s64) = G_ADD %0, %1 149 $x0 = COPY %2(s64) 150... 151 152--- 153name: add_neg_invalid_immed_s32 154legalized: true 155regBankSelected: true 156 157registers: 158 - { id: 0, class: gpr } 159 - { id: 1, class: gpr } 160 - { id: 2, class: gpr } 161 162body: | 163 bb.0: 164 liveins: $x0, $x1 165 ; We can't select this if the value is out of range. 166 ; CHECK-LABEL: name: add_neg_invalid_immed_s32 167 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 168 ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000 169 ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]] 170 ; CHECK: $x0 = COPY [[ADDXrr]] 171 %0(s64) = COPY $x0 172 %1(s64) = G_CONSTANT i64 -5000 173 %2(s64) = G_ADD %0, %1 174 $x0 = COPY %2(s64) 175... 176 177--- 178name: add_neg_invalid_immed_s64 179legalized: true 180regBankSelected: true 181 182registers: 183 - { id: 0, class: gpr } 184 - { id: 1, class: gpr } 185 - { id: 2, class: gpr } 186 187body: | 188 bb.0: 189 liveins: $x0, $x1 190 ; We can't select this if the value is out of range. 191 ; CHECK-LABEL: name: add_neg_invalid_immed_s64 192 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 193 ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000 194 ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]] 195 ; CHECK: $x0 = COPY [[ADDXrr]] 196 %0(s64) = COPY $x0 197 %1(s64) = G_CONSTANT i64 -5000 198 %2(s64) = G_ADD %0, %1 199 $x0 = COPY %2(s64) 200... 201 202--- 203name: add_imm_0_s32 204legalized: true 205regBankSelected: true 206 207registers: 208 - { id: 0, class: gpr } 209 - { id: 1, class: gpr } 210 - { id: 2, class: gpr } 211 212body: | 213 bb.0: 214 liveins: $x0, $x1 215 ; We shouldn't get a SUB here, because "cmp wN, $0" and "cmp wN, #0" have 216 ; opposite effects on the C flag. 217 ; CHECK-LABEL: name: add_imm_0_s32 218 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 219 ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0 220 ; CHECK: $x0 = COPY [[ADDXri]] 221 %0(s64) = COPY $x0 222 %1(s64) = G_CONSTANT i64 0 223 %2(s64) = G_ADD %0, %1 224 $x0 = COPY %2(s64) 225... 226 227--- 228name: add_imm_0_s64 229legalized: true 230regBankSelected: true 231 232registers: 233 - { id: 0, class: gpr } 234 - { id: 1, class: gpr } 235 - { id: 2, class: gpr } 236 237body: | 238 bb.0: 239 liveins: $x0, $x1 240 ; We shouldn't get a SUB here, because "cmp xN, $0" and "cmp xN, #0" have 241 ; opposite effects on the C flag. 242 ; CHECK-LABEL: name: add_imm_0_s64 243 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 244 ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0 245 ; CHECK: $x0 = COPY [[ADDXri]] 246 %0(s64) = COPY $x0 247 %1(s64) = G_CONSTANT i64 0 248 %2(s64) = G_ADD %0, %1 249 $x0 = COPY %2(s64) 250... 251 252--- 253name: add_imm_s32_gpr_bb 254legalized: true 255regBankSelected: true 256 257registers: 258 - { id: 0, class: gpr } 259 - { id: 1, class: gpr } 260 - { id: 2, class: gpr } 261 262body: | 263 ; CHECK-LABEL: name: add_imm_s32_gpr_bb 264 ; CHECK: bb.0: 265 ; CHECK: successors: %bb.1(0x80000000) 266 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 267 ; CHECK: B %bb.1 268 ; CHECK: bb.1: 269 ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 270 ; CHECK: $w0 = COPY [[ADDWri]] 271 bb.0: 272 liveins: $w0, $w1 273 successors: %bb.1 274 275 %0(s32) = COPY $w0 276 %1(s32) = G_CONSTANT i32 1 277 G_BR %bb.1 278 279 bb.1: 280 %2(s32) = G_ADD %0, %1 281 $w0 = COPY %2(s32) 282... 283 284--- 285# Same as add_s32_gpr, for G_SUB operations. 286name: sub_s32_gpr 287legalized: true 288regBankSelected: true 289 290registers: 291 - { id: 0, class: gpr } 292 - { id: 1, class: gpr } 293 - { id: 2, class: gpr } 294 295body: | 296 bb.0: 297 liveins: $w0, $w1 298 299 ; CHECK-LABEL: name: sub_s32_gpr 300 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 301 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 302 ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv 303 ; CHECK: $w0 = COPY [[SUBSWrr]] 304 %0(s32) = COPY $w0 305 %1(s32) = COPY $w1 306 %2(s32) = G_SUB %0, %1 307 $w0 = COPY %2(s32) 308... 309 310--- 311# Same as add_s64_gpr, for G_SUB operations. 312name: sub_s64_gpr 313legalized: true 314regBankSelected: true 315 316registers: 317 - { id: 0, class: gpr } 318 - { id: 1, class: gpr } 319 - { id: 2, class: gpr } 320 321body: | 322 bb.0: 323 liveins: $x0, $x1 324 325 ; CHECK-LABEL: name: sub_s64_gpr 326 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 327 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 328 ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv 329 ; CHECK: $x0 = COPY [[SUBSXrr]] 330 %0(s64) = COPY $x0 331 %1(s64) = COPY $x1 332 %2(s64) = G_SUB %0, %1 333 $x0 = COPY %2(s64) 334... 335 336--- 337# Same as add_s32_gpr, for G_OR operations. 338name: or_s32_gpr 339legalized: true 340regBankSelected: true 341 342registers: 343 - { id: 0, class: gpr } 344 - { id: 1, class: gpr } 345 - { id: 2, class: gpr } 346 347body: | 348 bb.0: 349 liveins: $w0, $w1 350 351 ; CHECK-LABEL: name: or_s32_gpr 352 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 353 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 354 ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]] 355 ; CHECK: $w0 = COPY [[ORRWrr]] 356 %0(s32) = COPY $w0 357 %1(s32) = COPY $w1 358 %2(s32) = G_OR %0, %1 359 $w0 = COPY %2(s32) 360... 361 362--- 363# Same as add_s64_gpr, for G_OR operations. 364name: or_s64_gpr 365legalized: true 366regBankSelected: true 367 368registers: 369 - { id: 0, class: gpr } 370 - { id: 1, class: gpr } 371 - { id: 2, class: gpr } 372 373body: | 374 bb.0: 375 liveins: $x0, $x1 376 377 ; CHECK-LABEL: name: or_s64_gpr 378 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 379 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 380 ; CHECK: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]] 381 ; CHECK: $x0 = COPY [[ORRXrr]] 382 %0(s64) = COPY $x0 383 %1(s64) = COPY $x1 384 %2(s64) = G_OR %0, %1 385 $x0 = COPY %2(s64) 386... 387 388--- 389# 64-bit G_OR on vector registers. 390name: or_v2s32_fpr 391legalized: true 392regBankSelected: true 393# 394registers: 395 - { id: 0, class: fpr } 396 - { id: 1, class: fpr } 397 - { id: 2, class: fpr } 398 399# The actual OR does not matter as long as it is operating 400# on 64-bit width vector. 401body: | 402 bb.0: 403 liveins: $d0, $d1 404 405 ; CHECK-LABEL: name: or_v2s32_fpr 406 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 407 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 408 ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]] 409 ; CHECK: $d0 = COPY [[ORRv8i8_]] 410 %0(<2 x s32>) = COPY $d0 411 %1(<2 x s32>) = COPY $d1 412 %2(<2 x s32>) = G_OR %0, %1 413 $d0 = COPY %2(<2 x s32>) 414... 415 416--- 417# Same as add_s32_gpr, for G_AND operations. 418name: and_s32_gpr 419legalized: true 420regBankSelected: true 421 422registers: 423 - { id: 0, class: gpr } 424 - { id: 1, class: gpr } 425 - { id: 2, class: gpr } 426 427body: | 428 bb.0: 429 liveins: $w0, $w1 430 431 ; CHECK-LABEL: name: and_s32_gpr 432 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 433 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 434 ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]] 435 ; CHECK: $w0 = COPY [[ANDWrr]] 436 %0(s32) = COPY $w0 437 %1(s32) = COPY $w1 438 %2(s32) = G_AND %0, %1 439 $w0 = COPY %2(s32) 440... 441 442--- 443# Same as add_s64_gpr, for G_AND operations. 444name: and_s64_gpr 445legalized: true 446regBankSelected: true 447 448registers: 449 - { id: 0, class: gpr } 450 - { id: 1, class: gpr } 451 - { id: 2, class: gpr } 452 453body: | 454 bb.0: 455 liveins: $x0, $x1 456 457 ; CHECK-LABEL: name: and_s64_gpr 458 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 459 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 460 ; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]] 461 ; CHECK: $x0 = COPY [[ANDXrr]] 462 %0(s64) = COPY $x0 463 %1(s64) = COPY $x1 464 %2(s64) = G_AND %0, %1 465 $x0 = COPY %2(s64) 466... 467 468--- 469# Same as add_s32_gpr, for G_SHL operations. 470name: shl_s32_gpr 471legalized: true 472regBankSelected: true 473 474registers: 475 - { id: 0, class: gpr } 476 - { id: 1, class: gpr } 477 - { id: 2, class: gpr } 478 479body: | 480 bb.0: 481 liveins: $w0, $w1 482 483 ; CHECK-LABEL: name: shl_s32_gpr 484 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 485 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 486 ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]] 487 ; CHECK: $w0 = COPY [[LSLVWr]] 488 %0(s32) = COPY $w0 489 %1(s32) = COPY $w1 490 %2(s32) = G_SHL %0, %1 491 $w0 = COPY %2(s32) 492... 493 494--- 495name: shl_s32_64_gpr 496legalized: true 497regBankSelected: true 498 499registers: 500 - { id: 0, class: gpr } 501 - { id: 1, class: gpr } 502 - { id: 2, class: gpr } 503 504body: | 505 bb.0: 506 liveins: $w0, $x1 507 508 ; CHECK-LABEL: name: shl_s32_64_gpr 509 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 510 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x1 511 ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32 512 ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]] 513 ; CHECK: $w0 = COPY [[LSLVWr]] 514 %0(s32) = COPY $w0 515 %1(s64) = COPY $x1 516 %2(s32) = G_SHL %0, %1 517 $w0 = COPY %2(s32) 518... 519 520--- 521# Same as add_s64_gpr, for G_SHL operations. 522name: shl_s64_gpr 523legalized: true 524regBankSelected: true 525 526registers: 527 - { id: 0, class: gpr } 528 - { id: 1, class: gpr } 529 - { id: 2, class: gpr } 530 531body: | 532 bb.0: 533 liveins: $x0, $x1 534 535 ; CHECK-LABEL: name: shl_s64_gpr 536 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 537 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 538 ; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]] 539 ; CHECK: $x0 = COPY [[LSLVXr]] 540 %0(s64) = COPY $x0 541 %1(s64) = COPY $x1 542 %2(s64) = G_SHL %0, %1 543 $x0 = COPY %2(s64) 544... 545 546--- 547# Same as add_s32_gpr, for G_LSHR operations. 548name: lshr_s32_gpr 549legalized: true 550regBankSelected: true 551 552registers: 553 - { id: 0, class: gpr } 554 - { id: 1, class: gpr } 555 - { id: 2, class: gpr } 556 557body: | 558 bb.0: 559 liveins: $w0, $w1 560 561 ; CHECK-LABEL: name: lshr_s32_gpr 562 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 563 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 564 ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]] 565 ; CHECK: $w0 = COPY [[LSRVWr]] 566 %0(s32) = COPY $w0 567 %1(s32) = COPY $w1 568 %2(s32) = G_LSHR %0, %1 569 $w0 = COPY %2(s32) 570... 571 572--- 573# Same as add_s64_gpr, for G_LSHR operations. 574name: lshr_s64_gpr 575legalized: true 576regBankSelected: true 577 578registers: 579 - { id: 0, class: gpr } 580 - { id: 1, class: gpr } 581 - { id: 2, class: gpr } 582 583body: | 584 bb.0: 585 liveins: $x0, $x1 586 587 ; CHECK-LABEL: name: lshr_s64_gpr 588 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 589 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 590 ; CHECK: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]] 591 ; CHECK: $x0 = COPY [[LSRVXr]] 592 %0(s64) = COPY $x0 593 %1(s64) = COPY $x1 594 %2(s64) = G_LSHR %0, %1 595 $x0 = COPY %2(s64) 596... 597 598--- 599# Same as add_s32_gpr, for G_ASHR operations. 600name: ashr_s32_gpr 601legalized: true 602regBankSelected: true 603 604registers: 605 - { id: 0, class: gpr } 606 - { id: 1, class: gpr } 607 - { id: 2, class: gpr } 608 609body: | 610 bb.0: 611 liveins: $w0, $w1 612 613 ; CHECK-LABEL: name: ashr_s32_gpr 614 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 615 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 616 ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]] 617 ; CHECK: $w0 = COPY [[ASRVWr]] 618 %0(s32) = COPY $w0 619 %1(s32) = COPY $w1 620 %2(s32) = G_ASHR %0, %1 621 $w0 = COPY %2(s32) 622... 623 624--- 625# Same as add_s64_gpr, for G_ASHR operations. 626name: ashr_s64_gpr 627legalized: true 628regBankSelected: true 629 630registers: 631 - { id: 0, class: gpr } 632 - { id: 1, class: gpr } 633 - { id: 2, class: gpr } 634 635body: | 636 bb.0: 637 liveins: $x0, $x1 638 639 ; CHECK-LABEL: name: ashr_s64_gpr 640 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 641 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 642 ; CHECK: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]] 643 ; CHECK: $x0 = COPY [[ASRVXr]] 644 %0(s64) = COPY $x0 645 %1(s64) = COPY $x1 646 %2(s64) = G_ASHR %0, %1 647 $x0 = COPY %2(s64) 648... 649 650--- 651# Check that we select s32 GPR G_MUL. This is trickier than other binops because 652# there is only MADDWrrr, and we have to use the WZR physreg. 653name: mul_s32_gpr 654legalized: true 655regBankSelected: true 656 657registers: 658 - { id: 0, class: gpr } 659 - { id: 1, class: gpr } 660 - { id: 2, class: gpr } 661 662body: | 663 bb.0: 664 liveins: $w0, $w1 665 666 ; CHECK-LABEL: name: mul_s32_gpr 667 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 668 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 669 ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr 670 ; CHECK: $w0 = COPY [[MADDWrrr]] 671 %0(s32) = COPY $w0 672 %1(s32) = COPY $w1 673 %2(s32) = G_MUL %0, %1 674 $w0 = COPY %2(s32) 675... 676 677--- 678# Same as mul_s32_gpr for the s64 type. 679name: mul_s64_gpr 680legalized: true 681regBankSelected: true 682 683registers: 684 - { id: 0, class: gpr } 685 - { id: 1, class: gpr } 686 - { id: 2, class: gpr } 687 688body: | 689 bb.0: 690 liveins: $x0, $x1 691 692 ; CHECK-LABEL: name: mul_s64_gpr 693 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 694 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 695 ; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr 696 ; CHECK: $x0 = COPY [[MADDXrrr]] 697 %0(s64) = COPY $x0 698 %1(s64) = COPY $x1 699 %2(s64) = G_MUL %0, %1 700 $x0 = COPY %2(s64) 701... 702 703--- 704# Same as mul_s32_gpr for the s64 type. 705name: mulh_s64_gpr 706legalized: true 707regBankSelected: true 708 709 710body: | 711 bb.0: 712 liveins: $x0, $x1 713 714 ; CHECK-LABEL: name: mulh_s64_gpr 715 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 716 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 717 ; CHECK: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]] 718 ; CHECK: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]] 719 ; CHECK: $x0 = COPY [[SMULHrr]] 720 ; CHECK: $x0 = COPY [[UMULHrr]] 721 %0:gpr(s64) = COPY $x0 722 %1:gpr(s64) = COPY $x1 723 %2:gpr(s64) = G_SMULH %0, %1 724 %3:gpr(s64) = G_UMULH %0, %1 725 $x0 = COPY %2(s64) 726 $x0 = COPY %3(s64) 727... 728 729--- 730# Same as add_s32_gpr, for G_SDIV operations. 731name: sdiv_s32_gpr 732legalized: true 733regBankSelected: true 734 735registers: 736 - { id: 0, class: gpr } 737 - { id: 1, class: gpr } 738 - { id: 2, class: gpr } 739 740body: | 741 bb.0: 742 liveins: $w0, $w1 743 744 ; CHECK-LABEL: name: sdiv_s32_gpr 745 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 746 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 747 ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]] 748 ; CHECK: $w0 = COPY [[SDIVWr]] 749 %0(s32) = COPY $w0 750 %1(s32) = COPY $w1 751 %2(s32) = G_SDIV %0, %1 752 $w0 = COPY %2(s32) 753... 754 755--- 756# Same as add_s64_gpr, for G_SDIV operations. 757name: sdiv_s64_gpr 758legalized: true 759regBankSelected: true 760 761registers: 762 - { id: 0, class: gpr } 763 - { id: 1, class: gpr } 764 - { id: 2, class: gpr } 765 766body: | 767 bb.0: 768 liveins: $x0, $x1 769 770 ; CHECK-LABEL: name: sdiv_s64_gpr 771 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 772 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 773 ; CHECK: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]] 774 ; CHECK: $x0 = COPY [[SDIVXr]] 775 %0(s64) = COPY $x0 776 %1(s64) = COPY $x1 777 %2(s64) = G_SDIV %0, %1 778 $x0 = COPY %2(s64) 779... 780 781--- 782# Same as add_s32_gpr, for G_UDIV operations. 783name: udiv_s32_gpr 784legalized: true 785regBankSelected: true 786 787registers: 788 - { id: 0, class: gpr } 789 - { id: 1, class: gpr } 790 - { id: 2, class: gpr } 791 792body: | 793 bb.0: 794 liveins: $w0, $w1 795 796 ; CHECK-LABEL: name: udiv_s32_gpr 797 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 798 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 799 ; CHECK: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]] 800 ; CHECK: $w0 = COPY [[UDIVWr]] 801 %0(s32) = COPY $w0 802 %1(s32) = COPY $w1 803 %2(s32) = G_UDIV %0, %1 804 $w0 = COPY %2(s32) 805... 806 807--- 808# Same as add_s64_gpr, for G_UDIV operations. 809name: udiv_s64_gpr 810legalized: true 811regBankSelected: true 812 813registers: 814 - { id: 0, class: gpr } 815 - { id: 1, class: gpr } 816 - { id: 2, class: gpr } 817 818body: | 819 bb.0: 820 liveins: $x0, $x1 821 822 ; CHECK-LABEL: name: udiv_s64_gpr 823 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 824 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 825 ; CHECK: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]] 826 ; CHECK: $x0 = COPY [[UDIVXr]] 827 %0(s64) = COPY $x0 828 %1(s64) = COPY $x1 829 %2(s64) = G_UDIV %0, %1 830 $x0 = COPY %2(s64) 831... 832 833--- 834# Check that we select a s32 FPR G_FADD into FADDSrr. 835name: fadd_s32_fpr 836legalized: true 837regBankSelected: true 838 839registers: 840 - { id: 0, class: fpr } 841 - { id: 1, class: fpr } 842 - { id: 2, class: fpr } 843 844body: | 845 bb.0: 846 liveins: $s0, $s1 847 848 ; CHECK-LABEL: name: fadd_s32_fpr 849 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 850 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 851 ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]] 852 ; CHECK: $s0 = COPY [[FADDSrr]] 853 %0(s32) = COPY $s0 854 %1(s32) = COPY $s1 855 %2(s32) = G_FADD %0, %1 856 $s0 = COPY %2(s32) 857... 858 859--- 860name: fadd_s64_fpr 861legalized: true 862regBankSelected: true 863 864registers: 865 - { id: 0, class: fpr } 866 - { id: 1, class: fpr } 867 - { id: 2, class: fpr } 868 869body: | 870 bb.0: 871 liveins: $d0, $d1 872 873 ; CHECK-LABEL: name: fadd_s64_fpr 874 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 875 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 876 ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]] 877 ; CHECK: $d0 = COPY [[FADDDrr]] 878 %0(s64) = COPY $d0 879 %1(s64) = COPY $d1 880 %2(s64) = G_FADD %0, %1 881 $d0 = COPY %2(s64) 882... 883 884--- 885name: fsub_s32_fpr 886legalized: true 887regBankSelected: true 888 889registers: 890 - { id: 0, class: fpr } 891 - { id: 1, class: fpr } 892 - { id: 2, class: fpr } 893 894body: | 895 bb.0: 896 liveins: $s0, $s1 897 898 ; CHECK-LABEL: name: fsub_s32_fpr 899 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 900 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 901 ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]] 902 ; CHECK: $s0 = COPY [[FSUBSrr]] 903 %0(s32) = COPY $s0 904 %1(s32) = COPY $s1 905 %2(s32) = G_FSUB %0, %1 906 $s0 = COPY %2(s32) 907... 908 909--- 910name: fsub_s64_fpr 911legalized: true 912regBankSelected: true 913 914registers: 915 - { id: 0, class: fpr } 916 - { id: 1, class: fpr } 917 - { id: 2, class: fpr } 918 919body: | 920 bb.0: 921 liveins: $d0, $d1 922 923 ; CHECK-LABEL: name: fsub_s64_fpr 924 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 925 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 926 ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]] 927 ; CHECK: $d0 = COPY [[FSUBDrr]] 928 %0(s64) = COPY $d0 929 %1(s64) = COPY $d1 930 %2(s64) = G_FSUB %0, %1 931 $d0 = COPY %2(s64) 932... 933 934--- 935name: fmul_s32_fpr 936legalized: true 937regBankSelected: true 938 939registers: 940 - { id: 0, class: fpr } 941 - { id: 1, class: fpr } 942 - { id: 2, class: fpr } 943 944body: | 945 bb.0: 946 liveins: $s0, $s1 947 948 ; CHECK-LABEL: name: fmul_s32_fpr 949 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 950 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 951 ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]] 952 ; CHECK: $s0 = COPY [[FMULSrr]] 953 %0(s32) = COPY $s0 954 %1(s32) = COPY $s1 955 %2(s32) = G_FMUL %0, %1 956 $s0 = COPY %2(s32) 957... 958 959--- 960name: fmul_s64_fpr 961legalized: true 962regBankSelected: true 963 964registers: 965 - { id: 0, class: fpr } 966 - { id: 1, class: fpr } 967 - { id: 2, class: fpr } 968 969body: | 970 bb.0: 971 liveins: $d0, $d1 972 973 ; CHECK-LABEL: name: fmul_s64_fpr 974 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 975 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 976 ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]] 977 ; CHECK: $d0 = COPY [[FMULDrr]] 978 %0(s64) = COPY $d0 979 %1(s64) = COPY $d1 980 %2(s64) = G_FMUL %0, %1 981 $d0 = COPY %2(s64) 982... 983 984--- 985name: fdiv_s32_fpr 986legalized: true 987regBankSelected: true 988 989registers: 990 - { id: 0, class: fpr } 991 - { id: 1, class: fpr } 992 - { id: 2, class: fpr } 993 994body: | 995 bb.0: 996 liveins: $s0, $s1 997 998 ; CHECK-LABEL: name: fdiv_s32_fpr 999 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 1000 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 1001 ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]] 1002 ; CHECK: $s0 = COPY [[FDIVSrr]] 1003 %0(s32) = COPY $s0 1004 %1(s32) = COPY $s1 1005 %2(s32) = G_FDIV %0, %1 1006 $s0 = COPY %2(s32) 1007... 1008 1009--- 1010name: fdiv_s64_fpr 1011legalized: true 1012regBankSelected: true 1013 1014registers: 1015 - { id: 0, class: fpr } 1016 - { id: 1, class: fpr } 1017 - { id: 2, class: fpr } 1018 1019body: | 1020 bb.0: 1021 liveins: $d0, $d1 1022 1023 ; CHECK-LABEL: name: fdiv_s64_fpr 1024 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1025 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1026 ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]] 1027 ; CHECK: $d0 = COPY [[FDIVDrr]] 1028 %0(s64) = COPY $d0 1029 %1(s64) = COPY $d1 1030 %2(s64) = G_FDIV %0, %1 1031 $d0 = COPY %2(s64) 1032... 1033--- 1034name: add_v8i16 1035alignment: 4 1036legalized: true 1037regBankSelected: true 1038tracksRegLiveness: true 1039registers: 1040 - { id: 0, class: fpr } 1041 - { id: 1, class: fpr } 1042 - { id: 2, class: fpr } 1043machineFunctionInfo: {} 1044body: | 1045 bb.1: 1046 liveins: $q0, $q1 1047 1048 ; CHECK-LABEL: name: add_v8i16 1049 ; CHECK: liveins: $q0, $q1 1050 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1051 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1052 ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY]], [[COPY1]] 1053 ; CHECK: $q0 = COPY [[ADDv8i16_]] 1054 ; CHECK: RET_ReallyLR implicit $q0 1055 %0:fpr(<8 x s16>) = COPY $q0 1056 %1:fpr(<8 x s16>) = COPY $q1 1057 %2:fpr(<8 x s16>) = G_ADD %0, %1 1058 $q0 = COPY %2(<8 x s16>) 1059 RET_ReallyLR implicit $q0 1060 1061... 1062--- 1063name: add_v16i8 1064alignment: 4 1065legalized: true 1066regBankSelected: true 1067tracksRegLiveness: true 1068registers: 1069 - { id: 0, class: fpr } 1070 - { id: 1, class: fpr } 1071 - { id: 2, class: fpr } 1072machineFunctionInfo: {} 1073body: | 1074 bb.1: 1075 liveins: $q0, $q1 1076 1077 ; CHECK-LABEL: name: add_v16i8 1078 ; CHECK: liveins: $q0, $q1 1079 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1080 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1081 ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY]], [[COPY1]] 1082 ; CHECK: $q0 = COPY [[ADDv16i8_]] 1083 ; CHECK: RET_ReallyLR implicit $q0 1084 %0:fpr(<16 x s8>) = COPY $q0 1085 %1:fpr(<16 x s8>) = COPY $q1 1086 %2:fpr(<16 x s8>) = G_ADD %0, %1 1087 $q0 = COPY %2(<16 x s8>) 1088 RET_ReallyLR implicit $q0 1089 1090... 1091--- 1092name: add_v4i16 1093legalized: true 1094regBankSelected: true 1095tracksRegLiveness: true 1096body: | 1097 bb.1: 1098 liveins: $d0, $d1 1099 1100 ; CHECK-LABEL: name: add_v4i16 1101 ; CHECK: liveins: $d0, $d1 1102 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1103 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1104 ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY]], [[COPY1]] 1105 ; CHECK: $d0 = COPY [[ADDv4i16_]] 1106 ; CHECK: RET_ReallyLR implicit $d0 1107 %0:fpr(<4 x s16>) = COPY $d0 1108 %1:fpr(<4 x s16>) = COPY $d1 1109 %2:fpr(<4 x s16>) = G_ADD %0, %1 1110 $d0 = COPY %2(<4 x s16>) 1111 RET_ReallyLR implicit $d0 1112... 1113--- 1114name: or_v4i16 1115legalized: true 1116regBankSelected: true 1117tracksRegLiveness: true 1118body: | 1119 bb.1: 1120 liveins: $d0, $d1 1121 1122 ; CHECK-LABEL: name: or_v4i16 1123 ; CHECK: liveins: $d0, $d1 1124 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1125 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1126 ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]] 1127 ; CHECK: $d0 = COPY [[ORRv8i8_]] 1128 ; CHECK: RET_ReallyLR implicit $d0 1129 %0:fpr(<4 x s16>) = COPY $d0 1130 %1:fpr(<4 x s16>) = COPY $d1 1131 %2:fpr(<4 x s16>) = G_OR %0, %1 1132 $d0 = COPY %2(<4 x s16>) 1133 RET_ReallyLR implicit $d0 1134... 1135--- 1136name: xor_v4i16 1137legalized: true 1138regBankSelected: true 1139tracksRegLiveness: true 1140body: | 1141 bb.1: 1142 liveins: $d0, $d1 1143 1144 ; CHECK-LABEL: name: xor_v4i16 1145 ; CHECK: liveins: $d0, $d1 1146 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1147 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1148 ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY]], [[COPY1]] 1149 ; CHECK: $d0 = COPY [[EORv8i8_]] 1150 ; CHECK: RET_ReallyLR implicit $d0 1151 %0:fpr(<4 x s16>) = COPY $d0 1152 %1:fpr(<4 x s16>) = COPY $d1 1153 %2:fpr(<4 x s16>) = G_XOR %0, %1 1154 $d0 = COPY %2(<4 x s16>) 1155 RET_ReallyLR implicit $d0 1156... 1157--- 1158name: mul_v4i16 1159legalized: true 1160regBankSelected: true 1161tracksRegLiveness: true 1162body: | 1163 bb.1: 1164 liveins: $d0, $d1 1165 1166 ; CHECK-LABEL: name: mul_v4i16 1167 ; CHECK: liveins: $d0, $d1 1168 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1169 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1170 ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY]], [[COPY1]] 1171 ; CHECK: $d0 = COPY [[MULv4i16_]] 1172 ; CHECK: RET_ReallyLR implicit $d0 1173 %0:fpr(<4 x s16>) = COPY $d0 1174 %1:fpr(<4 x s16>) = COPY $d1 1175 %2:fpr(<4 x s16>) = G_MUL %0, %1 1176 $d0 = COPY %2(<4 x s16>) 1177 RET_ReallyLR implicit $d0 1178... 1179