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Searched refs:buildMerge (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DMachineIRBuilderTest.cpp200 auto Merge = B.buildMerge(S128, {Copies[0], Copies[1]}); in TEST_F()
340 B.buildMerge(LLT::scalar(128), {RegC0, RegC1, RegC2, RegC3}); in TEST_F()
344 B.buildMerge(V2x32, {RegC0, RegC1}).getReg(0); in TEST_F()
346 B.buildMerge(V2x32, {RegC2, RegC3}).getReg(0); in TEST_F()
348 B.buildMerge(LLT::fixed_vector(4, 32), {RegC0C1, RegC2C3}); in TEST_F()
H A DLegalizerHelperTest.cpp1787 auto Merge0 = B.buildMerge(S24, Merge0Ops); in TEST_F()
1796 auto Merge1 = B.buildMerge(S21, Merge1Ops); in TEST_F()
1802 auto Merge2 = B.buildMerge(S16, Merge2Ops); in TEST_F()
1880 auto Merge = B.buildMerge(P0, {Lo, Hi}); in TEST_F()
2090 auto MIBMerge = B.buildMerge(S128, {Copies[1], Copies[2]}); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp414 MIRBuilder.buildMerge(Val, {Load_P2Half, Load_Rem}); in legalizeCustom()
416 auto Merge = MIRBuilder.buildMerge(s64, {Load_P2Half, Load_Rem}); in legalizeCustom()
443 auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)}); in legalizeCustom()
H A DMipsCallLowering.cpp184 MIRBuilder.buildMerge(Arg.OrigRegs[0], {CopyLo, CopyHi}); in assignCustomValue()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp258 MIRBuilder.buildMerge(DstReg, PartRegs); in insertParts()
307 MIRBuilder.buildMerge(DstReg, AllElts); in mergeMixedSubvectors()
443 MIRBuilder.buildMerge(DstReg, RemergeRegs); in buildWidenedRemergeToDst()
939 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
1363 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
2678 MIRBuilder.buildMerge(Dst, SrcRegs); in lowerBitcast()
2686 MIRBuilder.buildMerge(Dst, SrcRegs); in lowerBitcast()
5152 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalarMul()
5242 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalarExtract()
5327 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalarInsert()
[all …]
H A DCallLowering.cpp295 B.buildMerge(LCMTy, SrcRegs)); in mergeVectorRegsToResultRegs()
376 B.buildMerge(OrigRegs[0], Regs); in buildCopyFromRegs()
378 auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs); in buildCopyFromRegs()
446 auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt)); in buildCopyFromRegs()
528 UnmergeSrc = B.buildMerge(LCMTy, MergeParts).getReg(0); in buildCopyToRegs()
H A DMachineIRBuilder.cpp236 return buildMerge(Res, Regs); in buildPadVectorWithUndefElements()
255 return buildMerge(Res, Regs); in buildDeleteTrailingVectorElements()
590 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge() function in MachineIRBuilder
601 MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge() function in MachineIRBuilder
H A DCombinerHelper.cpp388 Builder.buildMerge(NewDstReg, Ops); in applyCombineShuffleVector()
1950 Builder.buildMerge(DstReg, { Narrowed, Zero }); in applyCombineShiftToUnmerge()
1963 Builder.buildMerge(DstReg, { Zero, Narrowed }); in applyCombineShiftToUnmerge()
1973 Builder.buildMerge(DstReg, { Unmerge.getReg(1), Hi }); in applyCombineShiftToUnmerge()
1979 Builder.buildMerge(DstReg, { Hi, Hi }); in applyCombineShiftToUnmerge()
1987 Builder.buildMerge(DstReg, { Lo, Hi }); in applyCombineShiftToUnmerge()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2034 B.buildMerge(Dst, {Src, HighAddr}); in legalizeAddrSpaceCast()
2303 Sign = B.buildMerge(S64, {Sign, Sign}); in legalizeFPTOI()
2307 B.buildMerge(Dst, {Lo, Hi}); in legalizeFPTOI()
2399 B.buildMerge(Dst, SrcRegs); in legalizeInsertVectorElt()
2898 auto Merge = B.buildMerge(S32, {Src0, Src1}); in legalizeBuildVector()
3191 B.buildMerge(DstReg, AccumRegs); in legalizeMul()
3540 auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi}); in legalizeUnsignedDIV_REM64Impl()
4602 B.buildMerge(Dst, Repack); in legalizeBufferLoad()
5438 auto Merged = B.buildMerge( in legalizeBVHIntrinsic()
5450 auto MergedDir = B.buildMerge( in legalizeBVHIntrinsic()
[all …]
H A DAMDGPURegisterBankInfo.cpp732 Register Dst = B.buildMerge(Ty, DstParts).getReg(0); in buildReadFirstLane()
1441 B.buildMerge(Dst, LoadParts); in applyMappingSBufferLoad()
1501 B.buildMerge(DstReg, {Extract, Extend}); in applyMappingBFE()
1510 B.buildMerge(DstReg, {UnmergeSOffset.getReg(0), Extract}); in applyMappingBFE()
1697 B.buildMerge(Dst0, {DstLo, DstHi}); in applyMappingMAD_64_32()
1784 return B.buildMerge(LLT::fixed_vector(NumElts, S32), WideRegs).getReg(0); in handleD16VData()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallLowering.cpp382 MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs); in lowerCall()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h303 Builder.buildMerge(DstReg, SrcRegs); in tryCombineTrunc()
971 Builder.buildMerge(DefReg, Regs); in tryCombineUnmergeValues()
H A DMachineIRBuilder.h970 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
971 MachineInstrBuilder buildMerge(const DstOp &Res,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp340 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs); in assignCustomValue()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1100 MIRBuilder.buildMerge(ValReg, {NewI->getOperand(0), NewI->getOperand(1)}); in legalizeLoadStore()
1384 MIRBuilder.buildMerge(MI.getOperand(0), {DstLo, DstHi}); in legalizeAtomicCmpxchg128()
H A DAArch64CallLowering.cpp415 MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0); in lowerReturn()