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Searched refs:buildBuildVector (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp69 B.buildBuildVector(v4s64, {Copies[0], Copies[0], Copies[0], Copies[0]}); in TEST_F()
573 B.buildBuildVector(v4s64, {Copies[0], Copies[0], Copies[0], Copies[0]}); in TEST_F()
604 B.buildBuildVector(v4s64, {Copies[0], Copies[0], Copies[0], Copies[0]}); in TEST_F()
679 auto ZeroSplat = B.buildBuildVector(v4s64, {FPZero, FPZero, FPZero, FPZero}); in TEST_F()
684 auto ZeroUndef = B.buildBuildVector(v4s64, {FPZero, FPZero, FPZero, Undef}); in TEST_F()
690 auto UndefSplat = B.buildBuildVector(v4s64, {Undef, Undef, Undef, Undef}); in TEST_F()
694 auto ZeroOne = B.buildBuildVector(v4s64, {FPZero, FPZero, FPZero, FPOne}); in TEST_F()
699 B.buildBuildVector(v4s64, {Copies[0], Copies[0], Copies[0], Copies[0]}); in TEST_F()
703 auto Mixed = B.buildBuildVector(v4s64, {FPZero, FPZero, FPZero, Copies[0]}); in TEST_F()
H A DCSETest.cpp189 auto BV = CSEB.buildBuildVector(VecTy, {Cst8.getReg(0), Cst16.getReg(0), in TEST_F()
H A DKnownBitsVectorTest.cpp625 B.buildBuildVector(V2S32, {B.buildConstant(S32, 1).getReg(0), in TEST_F()
628 B.buildBuildVector(V2S32, {B.buildConstant(S32, 0x80000000).getReg(0), in TEST_F()
633 B.buildBuildVector(V2S32, {B.buildConstant(S32, 0x80000000).getReg(0), in TEST_F()
H A DLegalizerHelperTest.cpp1729 auto BV0 = B.buildBuildVector(V2S16, {Constant0, Constant1}); in TEST_F()
1730 auto BV1 = B.buildBuildVector(V2S16, {Constant0, Constant1}); in TEST_F()
4046 auto V1 = B.buildBuildVector(V6S64, {Copies[0], Copies[1], Copies[0], in TEST_F()
4048 auto V2 = B.buildBuildVector(V6S64, {Copies[0], Copies[1], Copies[0], in TEST_F()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCSEMIRBuilder.cpp273 return buildBuildVector(DstOps[0], ConstantRegs); in buildInstr()
H A DCallLowering.cpp436 B.buildBuildVector(OrigRegs[0], Regs); in buildCopyFromRegs()
453 B.buildBuildVector(OrigRegs[0], EltMerges); in buildCopyFromRegs()
458 auto BV = B.buildBuildVector(BVType, Regs); in buildCopyFromRegs()
H A DCombinerHelper.cpp289 Builder.buildBuildVector(NewDstReg, Ops); in applyCombineConcatVectors()
2617 Builder.buildBuildVector(MI.getOperand(0).getReg(), MatchInfo); in applyCombineInsertVecElts()
4851 PreShift = MIB.buildBuildVector(ShiftAmtTy, PreShifts).getReg(0); in buildUDivUsingMul()
4852 MagicFactor = MIB.buildBuildVector(Ty, MagicFactors).getReg(0); in buildUDivUsingMul()
4853 NPQFactor = MIB.buildBuildVector(Ty, NPQFactors).getReg(0); in buildUDivUsingMul()
4854 PostShift = MIB.buildBuildVector(ShiftAmtTy, PostShifts).getReg(0); in buildUDivUsingMul()
H A DIRTranslator.cpp3049 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
3059 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
3076 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
H A DLegalizerHelper.cpp265 MIRBuilder.buildBuildVector(DstReg, PartRegs); in insertParts()
937 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
2774 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); in bitcastExtractVectorElt()
4373 Output = MIRBuilder.buildBuildVector(NarrowTy, SVOps).getReg(0); in fewerElementsVectorShuffle()
5240 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalarExtract()
6687 MIRBuilder.buildBuildVector(DstReg, BuildVec); in lowerShuffleVector()
H A DMachineIRBuilder.cpp634 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res, in buildBuildVector() function in MachineIRBuilder
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2742 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0); in legalizeAtomicCmpXChg()
4337 return B.buildBuildVector(LLT::fixed_vector(NumElts, S32), WideRegs) in handleD16VData()
4347 return B.buildBuildVector(LLT::fixed_vector(2, S32), PackedRegs) in handleD16VData()
4357 Reg = B.buildBuildVector(LLT::fixed_vector(6, S16), PackedRegs).getReg(0); in handleD16VData()
4368 return B.buildBuildVector(LLT::fixed_vector(4, S32), PackedRegs) in handleD16VData()
4777 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
4798 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
4802 B.buildBuildVector( in packImage16bitOpsToDwords()
4837 B.buildBuildVector(LLT::fixed_vector(NumAddrRegs, 32), AddrRegs); in convertImageAddrToPacked()
4940 auto Concat = B.buildBuildVector(PackedTy, {VData0, VData1}); in legalizeImageIntrinsic()
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H A DAMDGPURegisterBankInfo.cpp2099 B.buildBuildVector(MI.getOperand(0), Ops); in foldInsertEltToCmpSelect()
2101 auto Vec = B.buildBuildVector(MergeTy, Ops); in foldInsertEltToCmpSelect()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h644 return MIB.buildBuildVector(NewBVTy, NewSrcs).getReg(0); in findValueFromBuildVector()
H A DMachineIRBuilder.h999 MachineInstrBuilder buildBuildVector(const DstOp &Res,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp428 .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)}) in lowerReturn()