Searched refs:buildBitcast (Results 1 – 9 of 9) sorted by relevance
| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | LegalizerHelperTest.cpp | 1445 auto Val0 = B.buildBitcast(v2s32, Copies[0]); in TEST_F() 1446 auto Val1 = B.buildBitcast(v2s32, Copies[1]); in TEST_F() 1638 auto VecVal0 = B.buildBitcast(v2s32, Copies[0]); in TEST_F() 1639 auto VecVal1 = B.buildBitcast(v2s32, Copies[1]); in TEST_F() 3696 auto Vector = B.buildBitcast(V2S32, Copies[0]); in TEST_F() 3751 auto Vector = B.buildBitcast(V3S16, Trunc1); in TEST_F() 3829 auto Vector1 = B.buildBitcast(V2S32, Copies[0]); in TEST_F() 3830 auto Vector2 = B.buildBitcast(V4S16, Copies[0]); in TEST_F() 3880 auto Vector1 = B.buildBitcast(V2S32, Copies[0]); in TEST_F() 4146 auto Val0 = B.buildBitcast(v2s32, Copies[0]); in TEST_F() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPreLegalizerCombiner.cpp | 145 auto Bitcast = B.buildBitcast({S32}, CvtPk); in applyClampI64ToI16()
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| H A D | AMDGPULegalizerInfo.cpp | 2899 B.buildBitcast(Dst, Merge); in legalizeBuildVector() 4344 Reg = B.buildBitcast(S32, Reg).getReg(0); in handleD16VData() 4358 return B.buildBitcast(LLT::fixed_vector(3, S32), Reg).getReg(0); in handleD16VData() 4363 Reg = B.buildBitcast(LLT::fixed_vector(2, S32), Reg).getReg(0); in handleD16VData() 4783 AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0); in packImage16bitOpsToDwords() 5148 B.buildBitcast(DstReg, ResultRegs[0]); in legalizeImageIntrinsic() 5162 Reg = B.buildBitcast(V2S16, Reg).getReg(0); in legalizeImageIntrinsic() 5452 {B.buildBitcast(S32, B.buildMerge(V2S16, {UnmergeRayInvDir.getReg(0), in legalizeBVHIntrinsic() 5455 B.buildBitcast(S32, B.buildMerge(V2S16, {UnmergeRayInvDir.getReg(1), in legalizeBVHIntrinsic() 5458 B.buildBitcast(S32, B.buildMerge(V2S16, {UnmergeRayInvDir.getReg(2), in legalizeBVHIntrinsic()
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| H A D | AMDGPURegisterBankInfo.cpp | 1730 auto Bitcast = B.buildBitcast(S32, Src); in unpackV2S16ToS32() 2103 B.buildBitcast(MI.getOperand(0).getReg(), Vec); in foldInsertEltToCmpSelect() 2675 B.buildBitcast(DstReg, Or); in applyMappingImpl() 2754 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl() 2872 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl() 2907 B.buildBitcast(DstReg, InsHi); in applyMappingImpl() 2924 B.buildBitcast(DstReg, InsHi); in applyMappingImpl()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 335 B.buildBitcast(OrigRegs[0], Regs[0]); in buildCopyFromRegs() 397 CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0); in buildCopyFromRegs() 411 CastRegs[I++] = B.buildBitcast(GCDTy, SrcReg).getReg(0); in buildCopyFromRegs()
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| H A D | LegalizerHelper.cpp | 1430 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); in coerceToScalar() 1484 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); in bitcastSrc() 1491 MIRBuilder.buildBitcast(MO, CastDst); in bitcastDst() 2674 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); in lowerBitcast() 2739 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastExtractVectorElt() 2775 MIRBuilder.buildBitcast(Dst, NewVec); in bitcastExtractVectorElt() 2884 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastInsertVectorElt() 2918 MIRBuilder.buildBitcast(Dst, InsertedElt); in bitcastInsertVectorElt() 6770 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); in lowerExtract()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1132 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore() 1136 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore() 1243 Val = MIRBuilder.buildBitcast(VTy, Val).getReg(0); in legalizeCTPOP()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 130 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 668 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) { in buildBitcast() function
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