| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2711 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); in getBitcastWiderVectorElementOffset()
5632 auto MIBTmp = MIRBuilder.buildAnd( in lowerBitCount()
5788 ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0); in lowerFunnelShiftAsShifts()
5962 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); in lowerU64ToF32BitOps()
5965 auto T = MIRBuilder.buildAnd(S64, U, Mask1); in lowerU64ToF32BitOps()
5976 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); in lowerU64ToF32BitOps()
6199 auto MaskedSig = MIRBuilder.buildAnd(S32, UH, in lowerFPTRUNC_F64_TO_F16()
6475 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); in lowerFFloor()
6718 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); in lowerDynStackAlloc()
6871 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); in lowerInsert()
[all …]
|
| H A D | CombinerHelper.cpp | 2784 B.buildAnd(Dst, R, B.buildConstant(Ty, C1 & C2)); in matchOverlappingAnd()
3100 Builder.buildAnd(DstReg, Src0, Add); in applySimplifyURemByPow2()
5606 MIB.buildAnd(DstReg, Cond, TrueReg); in matchSelectToLogical()
5622 MIB.buildAnd(DstReg, MIB.buildNot(OpTy, Cond), FalseReg); in matchSelectToLogical()
|
| H A D | MachineIRBuilder.cpp | 538 return buildAnd(Res, Op, Mask); in buildZExtInReg()
|
| H A D | IRTranslator.cpp | 1089 auto AndOp = MIB.buildAnd(SwitchTy, SwitchVal, CstMask); in emitBitTestCase()
2737 auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst); in translateAlloca()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PreLegalizerCombiner.cpp | 318 B.buildAnd( in tryToSimplifyUADDO()
|
| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | LegalizerHelperTest.cpp | 1395 auto And = B.buildAnd(V5S32, Op0, Op1); in TEST_F()
1448 auto And = B.buildAnd(v2s32, Val0, Val1); in TEST_F()
1537 B.buildAnd(PhiTy, Phi.getReg(0), Phi.getReg(0)); in TEST_F()
3552 auto And = B.buildAnd(V4S8, Val0, Val1); in TEST_F()
|
| H A D | PatternMatchTest.cpp | 176 auto MIBAnd = B.buildAnd(s64, Copies[0], Copies[1]); in TEST_F()
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 139 Builder.buildAnd(DstReg, SextSrc ? SextSrc : TruncSrc, Mask); in tryCombineZExt()
|
| H A D | MachineIRBuilder.h | 1591 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, in buildAnd() function
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 909 CondReg = B.buildAnd(S1, CondReg, CmpReg).getReg(0); in executeInWaterfallLoop()
1535 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask); in applyMappingBFE()
1740 auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff)); in unpackV2S16ToS32()
2668 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0); in applyMappingImpl()
|
| H A D | AMDGPULegalizerInfo.cpp | 2095 auto And = B.buildAnd(S1, Lt0, NeTrunc); in legalizeFceil()
2160 auto SignBit = B.buildAnd(S32, Hi, SignBitMask); in legalizeIntrinsicTrunc()
2171 auto Tmp0 = B.buildAnd(S64, Src, Not); in legalizeIntrinsicTrunc()
3294 B.buildAnd(DstReg, AndMaskSrc, B.buildConstant(S32, Mask >> Shift)); in loadInputValue()
|