2711   auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask);  in getBitcastWiderVectorElementOffset()
2850   auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask);  in buildBitFieldInsert()
3572     return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0);  in clampDynamicVectorIndex()
5632     auto MIBTmp = MIRBuilder.buildAnd(  in lowerBitCount()
5661     auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0);  in lowerBitCount()
5670     auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0);  in lowerBitCount()
5671     auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0);  in lowerBitCount()
5684     auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0);  in lowerBitCount()
5788       ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0);  in lowerFunnelShiftAsShifts()
5791       InvShAmt = MIRBuilder.buildAnd(ShTy, NotZ, Mask).getReg(0);  in lowerFunnelShiftAsShifts()
5904     auto ShAmt = MIRBuilder.buildAnd(AmtTy, Amt, BitWidthMinusOneC);  in lowerRotate()
5906     auto RevAmt = MIRBuilder.buildAnd(AmtTy, NegAmt, BitWidthMinusOneC);  in lowerRotate()
5962   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);  in lowerU64ToF32BitOps()
5965   auto T = MIRBuilder.buildAnd(S64, U, Mask1);  in lowerU64ToF32BitOps()
5976   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);  in lowerU64ToF32BitOps()
6123   auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask);  in lowerFPTOSI()
6128   auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask);  in lowerFPTOSI()
6134   auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask);  in lowerFPTOSI()
6189   E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask));  in lowerFPTRUNC_F64_TO_F16()
6197   M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe));  in lowerFPTRUNC_F64_TO_F16()
6199   auto MaskedSig = MIRBuilder.buildAnd(S32, UH,  in lowerFPTRUNC_F64_TO_F16()
6240   auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7));  in lowerFPTRUNC_F64_TO_F16()
6265   Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000));  in lowerFPTRUNC_F64_TO_F16()
6353   Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0);  in lowerFCopySign()
6356     And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0);  in lowerFCopySign()
6361     And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0);  in lowerFCopySign()
6366     And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0);  in lowerFCopySign()
6475   auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc);  in lowerFFloor()
6718     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);  in lowerDynStackAlloc()
6871   auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);  in lowerInsert()
7115     auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);  in lowerBswap()
7120     auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);  in lowerBswap()
7135   auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N);  in SwapN()
7136   auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0);  in SwapN()
7257   auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg);  in lowerSelect()
7258   auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask);  in lowerSelect()