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/llvm-project-15.0.7/clang/test/CodeGenCUDA/Inputs/
H A Dcuda.h33 int hipConfigureCall(dim3 gridSize, dim3 blockSize, size_t sharedSize = 0,
35 extern "C" hipError_t __hipPushCallConfiguration(dim3 gridSize, dim3 blockSize,
52 extern "C" int cudaConfigureCall(dim3 gridSize, dim3 blockSize,
55 extern "C" int __cudaPushCallConfiguration(dim3 gridSize, dim3 blockSize,
/llvm-project-15.0.7/clang/test/SemaCUDA/Inputs/
H A Dcuda.h24 int hipConfigureCall(dim3 gridSize, dim3 blockSize, size_t sharedSize = 0,
26 extern "C" hipError_t __hipPushCallConfiguration(dim3 gridSize, dim3 blockSize,
37 extern "C" int cudaConfigureCall(dim3 gridSize, dim3 blockSize,
40 extern "C" int __cudaPushCallConfiguration(dim3 gridSize, dim3 blockSize,
/llvm-project-15.0.7/clang/test/AST/Inputs/
H A Dcuda.h24 int hipConfigureCall(dim3 gridSize, dim3 blockSize, size_t sharedSize = 0,
26 extern "C" hipError_t __hipPushCallConfiguration(dim3 gridSize, dim3 blockSize,
37 extern "C" int cudaConfigureCall(dim3 gridSize, dim3 blockSize,
40 extern "C" int __cudaPushCallConfiguration(dim3 gridSize, dim3 blockSize,
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-nounrolledremainder.ll52 %cmp.not6 = icmp eq i32 %blockSize, 0
56 %scevgep = getelementptr half, half* %pDst, i32 %blockSize
57 %scevgep14 = getelementptr half, half* %pSrcA, i32 %blockSize
69 %n.rnd.up = add i32 %blockSize, 7
175 %cmp.not6 = icmp eq i32 %blockSize, 0
179 %min.iters.check = icmp ult i32 %blockSize, 8
183 %scevgep = getelementptr half, half* %pDst, i32 %blockSize
196 %n.vec = and i32 %blockSize, -8
197 %ind.end = and i32 %blockSize, 7
220 %cmp.n = icmp eq i32 %n.vec, %blockSize
[all …]
H A Dmve-pred-vctpvpsel.ll4 define void @arm_min_helium_f32(float* %pSrc, i32 %blockSize, float* nocapture %pResult, i32* nocap…
50 %blkCnt.0 = phi i32 [ %blockSize, %entry ], [ %sub, %do.body ]
72 %.splatinsert1 = insertelement <4 x i32> undef, i32 %blockSize, i32 0
75 %16 = tail call i32 @llvm.arm.mve.minv.v4i32(i32 %blockSize, <4 x i32> %15, i32 1)
H A Dmve-sext-masked-load.ll5 define arm_aapcs_vfpcc <4 x float> @foo_v4i16(<4 x i16>* nocapture readonly %pSrc, i32 %blockSize, …
20 define arm_aapcs_vfpcc <8 x half> @foo_v8i8(<8 x i8>* nocapture readonly %pSrc, i32 %blockSize, <8 …
35 define arm_aapcs_vfpcc <4 x float> @foo_v4i8(<4 x i8>* nocapture readonly %pSrc, i32 %blockSize, <4…
51 define arm_aapcs_vfpcc <4 x double> @foo_v4i32(<4 x i32>* nocapture readonly %pSrc, i32 %blockSize,…
H A Dmve-zext-masked-load.ll19 define arm_aapcs_vfpcc <8 x half> @foo_v8i8(<8 x i8>* nocapture readonly %pSrc, i32 %blockSize, <8 …
34 define arm_aapcs_vfpcc <4 x float> @foo_v4i8(<4 x i8>* nocapture readonly %pSrc, i32 %blockSize, <4…
50 define arm_aapcs_vfpcc <4 x double> @foo_v4i32(<4 x i32>* nocapture readonly %pSrc, i32 %blockSize,…
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dpredicated-liveout-unknown-lanes.ll4 define arm_aapcs_vfpcc <4 x float> @arm_max_no_idx_f32_mve(float* %pSrc, i32 %blockSize, float* noc…
25 %blockSize.addr.0 = phi i32 [ %blockSize, %entry ], [ %sub, %do.body ]
28 %0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blockSize.addr.0)
33 %sub = add i32 %blockSize.addr.0, -4
H A Dtail-pred-intrinsic-add-sat.ll4 …nly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
24 %cmp7 = icmp eq i32 %blockSize, 0
28 %n.rnd.up = add i32 %blockSize, 7
37 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
53 …nly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
73 %cmp7 = icmp eq i32 %blockSize, 0
77 %n.rnd.up = add i32 %blockSize, 7
86 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
H A Dtail-pred-intrinsic-sub-sat.ll4 …nly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
24 %cmp7 = icmp eq i32 %blockSize, 0
28 %n.rnd.up = add i32 %blockSize, 7
37 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
53 …nly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
73 %cmp7 = icmp eq i32 %blockSize, 0
77 %n.rnd.up = add i32 %blockSize, 7
86 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
H A Dminloop.ll4 define void @arm_min_q31(i32* nocapture readonly %pSrc, i32 %blockSize, i32* nocapture %pResult, i3…
83 %blkCnt.015 = add i32 %blockSize, -1
88 %1 = add i32 %blockSize, -2
106 %sub3 = sub i32 %blockSize, %blkCnt.020
113 %sub3.1 = sub i32 %blockSize, %blkCnt.0
120 %sub3.2 = sub i32 %blockSize, %blkCnt.0.1
127 %sub3.3 = sub i32 %blockSize, %blkCnt.0.2
149 %sub3.epil = sub i32 %blockSize, %blkCnt.020.unr
167 %sub3.epil.1 = sub i32 %blockSize, %blkCnt.0.epil
178 %sub3.epil.2 = sub i32 %blockSize, %blkCnt.0.epil.1
H A Dtail-pred-intrinsic-fabs.ll4 …d @fabs(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %blockSize) {
23 %cmp3 = icmp eq i32 %blockSize, 0
27 %n.rnd.up = add i32 %blockSize, 3
35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %blockSize)
H A Dmov-operand.ll4 define arm_aapcs_vfpcc void @arm_var_f32_mve(float* %pSrc, i32 %blockSize, float* nocapture %pResul…
43 %blkCnt.0.i = phi i32 [ %sub.i, %do.body.i ], [ %blockSize, %entry ]
58 %conv.i = uitofp i32 %blockSize to float
65 %blkCnt.0 = phi i32 [ %blockSize, %arm_mean_f32_mve.exit ], [ %sub, %do.body ]
81 %sub2 = add i32 %blockSize, -1
H A Dremove-elem-moves.mir5 … @remove_mov_lr_chain(float* nocapture readonly %pSrc, float* nocapture %pDst, i32 %blockSize) #0 {
7 %cmp5 = icmp eq i32 %blockSize, 0
11 %min.iters.check = icmp ult i32 %blockSize, 4
15 %scevgep = getelementptr float, float* %pDst, i32 %blockSize
16 %scevgep12 = getelementptr float, float* %pSrc, i32 %blockSize
20 %0 = lshr i32 %blockSize, 2
28 %n.vec = and i32 %blockSize, -4
29 %ind.end = sub i32 %blockSize, %n.vec
55 %cmp.n = icmp eq i32 %n.vec, %blockSize
59 …%blkCnt.08.ph = phi i32 [ %blockSize, %vector.memcheck ], [ %blockSize, %while.body.preheader ], […
H A Dmov-after-dlstp.mir7 …define arm_aapcs_vfpcc void @arm_var_f32_mve(float* %pSrc, i32 %blockSize, float* nocapture %pResu…
9 %0 = add i32 %blockSize, 3
10 %1 = icmp slt i32 %blockSize, 4
11 %smin = select i1 %1, i32 %blockSize, i32 4
15 %5 = icmp slt i32 %blockSize, 4
16 %smin3 = select i1 %5, i32 %blockSize, i32 4
24 %blkCnt.0.i = phi i32 [ %13, %do.body.i ], [ %blockSize, %entry ]
41 %conv.i = uitofp i32 %blockSize to float
51 %blkCnt.0 = phi i32 [ %blockSize, %arm_mean_f32_mve.exit ], [ %26, %do.body ]
69 %sub2 = add i32 %blockSize, -1
H A Dunpredload.ll4 define void @arm_cmplx_mag_squared_q15_mve(i16* %pSrc, i16* %pDst, i32 %blockSize) {
26 %blockSize.addr.0 = phi i32 [ %blockSize, %entry ], [ %sub, %do.body ]
29 %0 = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %blockSize.addr.0)
41 %sub = add i32 %blockSize.addr.0, -8
/llvm-project-15.0.7/clang/test/SemaCUDA/
H A Dconfig-type.cu5 void cudaConfigureCall(unsigned gridSize, unsigned blockSize);
7 void __cudaPushCallConfiguration(unsigned gridSize, unsigned blockSize);
/llvm-project-15.0.7/mlir/lib/Dialect/Async/Transforms/
H A DAsyncParallelFor.cpp136 BlockArgument blockSize();
163 BlockArgument ParallelComputeFunctionArgs::blockSize() { return args[1]; } in blockSize() function in ParallelComputeFunctionArgs
283 BlockArgument blockSize = args.blockSize(); in createParallelComputeFunction() local
317 Value blockFirstIndex = b.create<arith::MulIOp>(blockIndex, blockSize); in createParallelComputeFunction()
321 Value blockEnd0 = b.create<arith::AddIOp>(blockFirstIndex, blockSize); in createParallelComputeFunction()
577 scf::ParallelOp op, Value blockSize, in doAsyncDispatch() argument
610 SmallVector<Value> operands = {c0, blockSize}; in doAsyncDispatch()
629 SmallVector<Value> operands = {group, c0, blockCount, blockSize}; in doAsyncDispatch()
672 SmallVector<Value> computeFuncOperands = {blockIndex, blockSize}; in doSequentialDispatch()
860 Value blockSize = b.create<arith::MinSIOp>(tripCount, bs1); in matchAndRewrite() local
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dssat-unroll-loops.ll6 define void @ssat_unroll(i16* %pSrcA, i16* %pSrcB, i16* %pDst, i32 %blockSize) {
47 %cmp.not7 = icmp eq i32 %blockSize, 0
51 %0 = add i32 %blockSize, -1
52 %xtraiter = and i32 %blockSize, 1
75 …%blkCnt.011.unr = phi i32 [ %blockSize, %while.body.preheader ], [ %0, %while.body.prol.preheader ]
125 … readonly %pSrcA, i16* nocapture readonly %pSrcB, i16* nocapture writeonly %pDst, i32 %blockSize) {
166 %cmp.not7 = icmp eq i32 %blockSize, 0
170 %0 = add i32 %blockSize, -1
171 %xtraiter = and i32 %blockSize, 1
192 …%blkCnt.011.unr = phi i32 [ %blockSize, %while.body.preheader ], [ %0, %while.body.prol.preheader ]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/ARM/
H A Darm_fill_q7.ll12 define dso_local void @arm_fill_q7(i8 signext %value, i8* %pDst, i32 %blockSize) #0 {
56 %blockSize.addr = alloca i32, align 4
61 store i32 %blockSize, i32* %blockSize.addr, align 4, !tbaa !8
86 %6 = load i32, i32* %blockSize.addr, align 4, !tbaa !8
105 %10 = load i32, i32* %blockSize.addr, align 4, !tbaa !8
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ARM/
H A Dmve-qabs.ll7 define void @arm_abs_q7(i8* nocapture readonly %pSrc, i8* nocapture %pDst, i32 %blockSize) #0 {
70 %cmp.not19 = icmp eq i32 %blockSize, 0
78 %blkCnt.021 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ]
100 define void @arm_abs_q15(i16* nocapture readonly %pSrc, i16* nocapture %pDst, i32 %blockSize) #0 {
163 %cmp.not20 = icmp eq i32 %blockSize, 0
171 %blkCnt.022 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ]
193 define void @arm_abs_q31(i32* nocapture readonly %pSrc, i32* nocapture %pDst, i32 %blockSize) #0 {
256 %cmp.not14 = icmp eq i32 %blockSize, 0
264 %blkCnt.016 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ]
H A Dmve-selectandorcost.ll14 define float @test(float* nocapture readonly %pA, float* nocapture readonly %pB, i32 %blockSize) #0…
93 %cmp.not16 = icmp eq i32 %blockSize, 0
99 %blockSize.addr.018 = phi i32 [ %dec, %if.end ], [ %blockSize, %entry ]
122 %dec = add i32 %blockSize.addr.018, -1
H A Dmve-saddsatcost.ll15 …* nocapture readonly %pSrc, i16 signext %offset, i16* nocapture noalias %pDst, i32 %blockSize) #0 {
43 %cmp.not6 = icmp eq i32 %blockSize, 0
47 %blkCnt.09 = phi i32 [ %dec, %while.body ], [ %blockSize, %entry ]
H A Dmve-icmpcost.ll97 …VF 1 For instruction: %blkCnt.012 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.pre…
118 …VF 2 For instruction: %blkCnt.012 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.pre…
139 …VF 4 For instruction: %blkCnt.012 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.pre…
160 …VF 8 For instruction: %blkCnt.012 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.pre…
203 …nocapture readonly %pSrcA, i8* nocapture readonly %pSrcB, i8* nocapture %pDst, i32 %blockSize) #0 {
205 %cmp.not8 = icmp eq i32 %blockSize, 0
212 %blkCnt.012 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ]
243 define void @floatcmp(float* nocapture readonly %pSrc, i32* nocapture %pDst, i32 %blockSize) #0 {
245 %cmp.not7 = icmp eq i32 %blockSize, 0
250 %blockSize.addr.09 = phi i32 [ %dec, %while.body ], [ %blockSize, %entry ]
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Dmax-backedge-taken-count-guard-info.ll994 define void @test_guard_uge(i32 %blockSize) {
1010 %shr = lshr i32 %blockSize, 2
1011 %guard = icmp uge i32 %blockSize, 4
1046 %shr = lshr i32 %blockSize, 2
1047 %guard = icmp ugt i32 %blockSize, 3
1082 %shr = lshr i32 %blockSize, 2
1083 %guard1 = icmp uge i32 %blockSize, 4
1087 %guard2 = icmp ule i32 %blockSize, 1024
1122 %shr = lshr i32 %blockSize, 2
1123 %guard1 = icmp ugt i32 %blockSize, 3
[all …]

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