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Searched refs:bitsLE (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h280 bool bitsLE(EVT VT) const { in bitsLE() function
H A DSelectionDAG.h827 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
843 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp1646 assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatRes_LOAD()
1683 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1695 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1699 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1715 if (isSigned || SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
2006 assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatOp_STORE()
H A DLegalizeVectorOps.cpp1007 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1066 if (SrcVT.bitsLE(VT)) { in ExpandZERO_EXTEND_VECTOR_INREG()
H A DLegalizeIntegerTypes.cpp746 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); in PromoteIntRes_INT_EXTEND()
3175 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ANY_EXTEND()
3542 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntRes_LOAD()
4260 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_SIGN_EXTEND()
4292 if (EVT.bitsLE(Lo.getValueType())) { in ExpandIntRes_SIGN_EXTEND_INREG()
4573 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ZERO_EXTEND()
5049 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntOp_STORE()
5219 assert(PromEltVT.bitsLE(NOutVTElem) && in PromoteIntRes_EXTRACT_SUBVECTOR()
H A DSelectionDAG.cpp1052 EltVT.bitsLE(Op.getValueType()))) && in VerifySDNode()
1381 if (VT.bitsLE(Op.getValueType())) in getBoolExtOrTrunc()
1398 assert(VT.bitsLE(OpVT) && "Not extending!"); in getZeroExtendInReg()
5310 assert(Operand.getValueType().bitsLE(VT) && in getNode()
5353 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && in getNode()
6070 VT.bitsLE(N1.getValueType()) && in getNode()
6084 assert(EVT.bitsLE(VT.getScalarType()) && "Not extending!"); in getNode()
6099 assert(EVT.bitsLE(VT) && "Not extending!"); in getNode()
6143 assert(cast<VTSDNode>(N2)->getVT().bitsLE(VT.getScalarType()) && in getNode()
H A DTargetLowering.cpp4441 isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && in SimplifySetCC()
4752 (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && in SimplifySetCC()
H A DLegalizeDAG.cpp2332 (DestVT.bitsLE(MVT::f64) || in ExpandLegalINT_TO_FP()
H A DDAGCombiner.cpp5810 if (ExtVT.bitsLE(Load->getMemoryVT())) in SearchForAndLoads()
21194 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT; in visitCONCAT_VECTORS()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DMachineValueType.h1170 bool bitsLE(MVT VT) const { in bitsLE() function
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td1140 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1144 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
H A DRISCVISelLowering.cpp2293 assert((ViaIntVT.bitsLE(XLenVT) || in lowerBUILD_VECTOR()
2296 if (ViaIntVT.bitsLE(XLenVT) || isInt<32>(SplatValue)) { in lowerBUILD_VECTOR()
2456 if (Scalar.getValueType().bitsLE(XLenVT)) { in lowerScalarSplat()
4910 if (Scalar.getValueType().bitsLE(XLenVT)) { in LowerINTRINSIC_WO_CHAIN()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1135 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
H A DAMDGPUISelLowering.cpp3307 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()
H A DSIISelLowering.cpp1588 VT.getScalarType().bitsLE(MVT::i16)) in getPreferredVectorAction()
5284 return Op.getValueType().bitsLE(VT) ? in getFPExtOrFPRound()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1376 return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020(); in decomposeMulByConstant()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp16877 AVT.bitsLE(Ty); in PerformVECREDUCE_ADDCombine()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp26324 assert(MaskVT.bitsLE(Mask.getSimpleValueType()) && "Unexpected mask size!"); in getMaskNode()