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/llvm-project-15.0.7/mlir/include/mlir/Dialect/X86Vector/
H A DTransforms.h51 template <unsigned b67, unsigned b45, unsigned b23, unsigned b01>
53 static_assert(b01 <= 0x03, "overflow"); in shuffle()
57 return static_cast<uint8_t>((b67 << 6) | (b45 << 4) | (b23 << 2) | b01); in shuffle()
60 static void extractShuffle(uint8_t mask, uint8_t &b01, uint8_t &b23, in extractShuffle()
65 b01 = mask & 0x03; in extractShuffle()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td45 let Inst{15, 14} = 0b01;
58 let Inst{15, 14} = 0b01;
71 let Inst{15, 14} = 0b01;
84 let Inst{15, 14} = 0b01;
96 let Inst{15, 14} = 0b01;
109 let Inst{15, 14} = 0b01;
120 let Inst{15, 14} = 0b01;
178 let Inst{15, 14} = 0b01;
216 let Inst{15, 14} = 0b01;
H A DCSKYInstrInfo16Instr.td65 def ADDC16 : R16_XZ_BINOP_C<0b1000, 0b01, "addc16">;
82 def LSR16 : R16_XZ_BINOP<0b1100, 0b01, "lsr16", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
86 def MULSH16 : R16_XZ_BINOP_NOPat<0b1111, 0b01, "mulsh16">;
89 def ZEXTH16 : R16_XZ_UNOP<0b1101, 0b01, "zexth16">;
179 let Inst{15,14} = 0b01;
190 let Inst{15,14} = 0b01;
218 def JSR16 : R16_X_J<0b11101111, 0b01, "jsr16"> {
290 let Inst{15, 14} = 0b01;
301 let Inst{15, 14} = 0b01;
324 let Inst{15,14} = 0b01;
[all …]
H A DCSKYInstrFormatsF2.td73 def _RZ : F2_XZ_P<datatype, {sop, 0b01}, op#".rz", [], outs, ins>;
137 : F2_LDST<0b01, sop, op#".64", outs, ins>;
157 : F2_LDSTM<0b01, sop, sop2, op#".64", outs, ins>;
181 : F2_LDSTR<0b01, sop, op#".64", outs, ins>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td367 def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">,
374 def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
383 def C_ADDI_NOP : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
400 def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
416 def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),
430 def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX0X2:$rd),
454 def C_XOR : CS_ALU<0b100011, 0b01, "c.xor", GPRC>,
464 def C_ADDW : CS_ALU<0b100111, 0b01, "c.addw", GPRC>,
628 def C_LUI_HINT : RVInst16CI<0b011, 0b01, (outs GPRX0:$rd),
671 def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
[all …]
H A DRISCVInstrInfoD.td105 defm FMADD_D : FPFMA_rrr_frm_m<OPC_MADD, 0b01, "fmadd.d", DINX>;
106 defm FMSUB_D : FPFMA_rrr_frm_m<OPC_MSUB, 0b01, "fmsub.d", DINX>;
107 defm FNMSUB_D : FPFMA_rrr_frm_m<OPC_NMSUB, 0b01, "fnmsub.d", DINX>;
108 defm FNMADD_D : FPFMA_rrr_frm_m<OPC_NMADD, 0b01, "fnmadd.d", DINX>;
H A DRISCVInstrFormatsV.td28 def MOPLDIndexedUnord : RISCVMOP<0b01>;
33 def MOPSTIndexedUnord : RISCVMOP<0b01>;
/llvm-project-15.0.7/llvm/unittests/TableGen/
H A DAutomata.td22 // Token SK_a sets bit 0b01.
23 def : SimpleTransition<0b01, SK_a>;
47 def : TupleTransition<0b01, SK_a, SK_b, "yeet">;
66 // Symbols a and b can transition to 0b01 or 0b11 (sets bit 0).
67 def : NfaTransition<0b01, SK_a>;
68 def : NfaTransition<0b01, SK_b>;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td428 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
472 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
507 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
520 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
541 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
548 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
849 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
972 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
1000 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
1014 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/X86/
H A Daddsub-inseltpoison.ll55 %b01 = extractelement <2 x float> %b0, i32 1
56 %add4 = fadd float %a01, %b01
86 %b01 = extractelement <2 x float> %b0, i32 1
87 %add4 = fadd float %a01, %b01
H A Daddsub.ll55 %b01 = extractelement <2 x float> %b0, i32 1
56 %add4 = fadd float %a01, %b01
86 %b01 = extractelement <2 x float> %b0, i32 1
87 %add4 = fadd float %a01, %b01
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dbitfield.cpp14 unsigned b01 : 2; member
52 return s->b01; in read01()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrVFP.td548 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
995 defm VCVTN : vcvt_inst<"n", 0b01>;
2107 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
2116 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
2129 def VNMLAH : AHbI<0b11100, 0b01, 1, 0,
2159 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
2168 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
2180 def VNMLSH : AHbI<0b11100, 0b01, 0, 0,
2304 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
2313 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
[all …]
H A DARMInstrNEON.td4024 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4041 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4061 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4078 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4100 let Inst{21-20} = 0b01; // imm6 = 01xxxx
5269 def VFMSLDI : VFMD<"vfmsl", "f16", 0b01>;
5271 def VFMSLQI : VFMQ<"vfmsl", "f16", 0b01>;
6115 def VABShd : N2VD<0b11, 0b11, 0b01, 0b01, 0b01110, 0,
6119 def VABShq : N2VQ<0b11, 0b11, 0b01, 0b01, 0b01110, 0,
6162 def VNEGhd : N2V<0b11, 0b11, 0b01, 0b01, 0b01111, 0, 0,
[all …]
H A DARMInstrMVE.td670 let Inst{17-16} = 0b01;
769 let Inst{17-16} = 0b01;
1521 let Inst{21-20} = 0b01;
1554 def MVE_VREV32_16 : MVE_VREV<"vrev32", "16", 0b01, 0b01, 0b10>;
1702 let Inst{7-6} = 0b01;
1815 let VecSize = 0b01;
2603 let Inst{7-6} = 0b01;
2847 let Inst{20-19} = 0b01;
2876 let Inst{17-16} = 0b01;
2957 let Inst{20-19} = 0b01;
[all …]
H A DARMInstrThumb2.td749 let Inst{26-25} = 0b01;
936 let Inst{25-24} = 0b01;
2132 let Inst{26-25} = 0b01;
2718 let Inst{26-25} = 0b01;
2735 let Inst{26-25} = 0b01;
2742 let Inst{7-6} = 0b01;
2750 let Inst{26-25} = 0b01;
2757 let Inst{7-6} = 0b01;
3278 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3304 let Inst{26-25} = 0b01;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td376 defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr", or>;
427 defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon", xor>;
880 defm LD1RH_IMM : sve_mem_ld_dup<0b01, 0b01, "ld1rh", Z_h, ZPR16, uimm6s2>;
974 defm LD2H_IMM : sve_mem_eld_si<0b01, 0b01, ZZ_h, "ld2h", simm4s2>;
988 def LD2H : sve_mem_eld_ss<0b01, 0b01, ZZ_h, "ld2h", GPR64NoXZRshifted16>;
1202 defm LDNT1H_ZRI : sve_mem_cldnt_si<0b01, "ldnt1h", Z_h, ZPR16>;
1217 defm ST1H_IMM : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>;
1369 defm ST2H_IMM : sve_mem_est_si<0b01, 0b01, ZZ_h, "st2h", simm4s2>;
1383 def ST2H : sve_mem_est_ss<0b01, 0b01, ZZ_h, "st2h", GPR64NoXZRshifted16>;
1395 defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>;
[all …]
H A DSVEInstrFormats.td1297 def _H : sve_int_perm_tbl<0b01, 0b01, asm, ZPR16, ZZ_h>;
1661 let Inst{15-14} = 0b01;
2485 let Inst{15-14} = 0b01;
2845 def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>,
2950 let Inst{15-14} = 0b01;
3430 let Inst{21-20} = 0b01;
4153 let Inst{21-20} = 0b01;
4602 let Inst{21-20} = 0b01;
4636 let Inst{21-20} = 0b01;
5554 let Inst{21-20} = 0b01;
[all …]
H A DAArch64InstrInfo.td2596 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16Op, "ldr", f16, load>;
2772 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16Op, uimm12s2, "ldr",
2869 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
2992 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16Op, "ldur",
3006 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
3190 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
3209 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16Op, "ldr">;
3224 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32z, "ldrh">;
3234 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16Op, "ldr">;
3249 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32z, "ldrh">;
[all …]
H A DAArch64InstrFormats.td1682 let Inst{20-19} = 0b01;
1697 let Inst{20-19} = 0b01;
3280 let Inst{25-24} = 0b01;
4130 let Inst{11-10} = 0b01;
5285 let Inst{11-10} = 0b01;
6870 let Inst{31-30} = 0b01;
6890 let Inst{31-30} = 0b01;
6983 let Inst{31-30} = 0b01;
7035 let Inst{31-30} = 0b01;
11508 def WTWN : MOPSMemoryCopy<opcode, 0b01, 0b01, asm # "wtwn">;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrFormats.td213 def MxEncEAj_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
214 def MxEncEAo_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
225 def MxEncEAj_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
226 def MxEncEAo_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
234 def MxEncEAj_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
235 def MxEncEAo_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
256 !eq(scale, 2) : 0b01,
456 def MxEncSize16 : MxEncSize<0b01>;
466 def MxNewEncSize16 : MxNewEncSize<0b01>;
H A DM68kInstrShiftRotate.td34 defvar MxROOP_LS = 0b01;
/llvm-project-15.0.7/mlir/lib/Dialect/X86Vector/Transforms/
H A DAVXTranspose.cpp66 uint8_t b01, b23, b45, b67; in mm256ShufflePs() local
67 MaskHelper::extractShuffle(mask, b01, b23, b45, b67); in mm256ShufflePs()
68 SmallVector<int64_t> shuffleMask{b01, b23, b45 + 8, b67 + 8, in mm256ShufflePs()
69 b01 + 4, b23 + 4, b45 + 8 + 4, b67 + 8 + 4}; in mm256ShufflePs()
/llvm-project-15.0.7/clang/test/OpenMP/
H A Ddeclare_simd_aarch64.c91 int b01(int *x);
177 *I = b01(I); in do_something()
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dcond-bitlist.td6 !eq(s, 16): 0b01,

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