Lines Matching refs:b01
289 def MVE_v8i16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "i", ?>;
297 def MVE_v8s16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "s", 0b0>;
301 def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "u", 0b1>;
306 def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1, v4i1, 0b01, "f", ?>;
477 def MVE_URSHR : MVE_ScalarShiftSRegImm<"urshr", 0b01>;
580 def MVE_LSRL : MVE_ScalarShiftDRegImm<"lsrl", 0b01, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
590 def MVE_URSHRL : MVE_ScalarShiftDRegImm<"urshrl", 0b01, 0b1>;
670 let Inst{17-16} = 0b01;
769 let Inst{17-16} = 0b01;
833 "$RdaDest = $RdaSrc", !if(sz, 0b01, 0b10), pattern> {
1396 defm MVE_VMLSLDAV : MVE_VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0, 0b01>;
1521 let Inst{21-20} = 0b01;
1550 def MVE_VREV64_16 : MVE_VREV<"vrev64", "16", 0b01, 0b00, 0b11, "@earlyclobber $Qd">;
1553 def MVE_VREV32_8 : MVE_VREV<"vrev32", "8", 0b00, 0b01, 0b10>;
1554 def MVE_VREV32_16 : MVE_VREV<"vrev32", "16", 0b01, 0b01, 0b10>;
1556 def MVE_VREV16_8 : MVE_VREV<"vrev16", "8", 0b00, 0b10, 0b01>;
1702 let Inst{7-6} = 0b01;
1815 let VecSize = 0b01;
2396 def MVE_VDUP16 : MVE_VDUP<"16", 0b0, 0b1, 0b01>;
2603 let Inst{7-6} = 0b01;
2615 def MVE_VMOVimmi16 : MVE_mod_imm<"vmov", "i16", {1,0,?,0}, 0b0, (ins nImmSplatI16:$imm), 0b01> {
2625 def MVE_VMVNimmi16 : MVE_mod_imm<"vmvn", "i16", {1,0,?,0}, 0b1, (ins nImmSplatI16:$imm), 0b01> {
2845 : MVE_VSHLL_imm<iname, suffix, U, th, mve_shift_imm1_7, 0b01, pattern> {
2847 let Inst{20-19} = 0b01;
2871 iname, suffix, ops, vpred_r, "", !if(size, 0b10, 0b01), pattern> {
2876 let Inst{17-16} = 0b01;
2894 defm MVE_VSHLL_lws16 : MVE_VSHLL_lw<"vshll", "s16", 0b01, 0b0, "$Qd, $Qm, #16">;
2896 defm MVE_VSHLL_lwu16 : MVE_VSHLL_lw<"vshll", "u16", 0b01, 0b1, "$Qd, $Qm, #16">;
2956 def MVE_VRSHRNi16bh : MVE_VxSHRN<"vrshrnb", "i16", 0b0, 0b1, shr_imm8, 0b01> {
2957 let Inst{20-19} = 0b01;
2959 def MVE_VRSHRNi16th : MVE_VxSHRN<"vrshrnt", "i16", 0b1, 0b1, shr_imm8, 0b01> {
2960 let Inst{20-19} = 0b01;
2969 def MVE_VSHRNi16bh : MVE_VxSHRN<"vshrnb", "i16", 0b0, 0b0, shr_imm8, 0b01> {
2970 let Inst{20-19} = 0b01;
2972 def MVE_VSHRNi16th : MVE_VxSHRN<"vshrnt", "i16", 0b1, 0b0, shr_imm8, 0b01> {
2973 let Inst{20-19} = 0b01;
3000 "vqrshrunb", "s16", 0b1, 0b0, shr_imm8, 0b01> {
3001 let Inst{20-19} = 0b01;
3004 "vqrshrunt", "s16", 0b1, 0b1, shr_imm8, 0b01> {
3005 let Inst{20-19} = 0b01;
3017 "vqshrunb", "s16", 0b0, 0b0, shr_imm8, 0b01> {
3018 let Inst{20-19} = 0b01;
3021 "vqshrunt", "s16", 0b0, 0b1, shr_imm8, 0b01> {
3022 let Inst{20-19} = 0b01;
3050 def s16 : MVE_VxQRSHRN<iname, "s16", bit_0, bit_12, shr_imm8, 0b01> {
3052 let Inst{20-19} = 0b01;
3054 def u16 : MVE_VxQRSHRN<iname, "u16", bit_0, bit_12, shr_imm8, 0b01> {
3056 let Inst{20-19} = 0b01;
3221 let Inst{7-6} = 0b01;
3255 def MVE_VSRIimm16 : MVE_VSxI_imm<"vsri", "16", 0b0, shr_imm16, 0b01> {
3256 let Inst{21-20} = 0b01;
3267 def MVE_VSLIimm16 : MVE_VSxI_imm<"vsli", "16", 0b1, imm0_15, 0b01> {
3268 let Inst{21-20} = 0b01;
3323 let Inst{21-20} = 0b01;
3326 let Inst{21-20} = 0b01;
3359 let Inst{21-20} = 0b01;
3394 let Inst{21-20} = 0b01;
3398 let Inst{21-20} = 0b01;
3465 def MVE_VSHR_imms16 : MVE_VSHR_imm<"s16", (ins shr_imm16:$imm), 0b01> {
3467 let Inst{21-20} = 0b01;
3470 def MVE_VSHR_immu16 : MVE_VSHR_imm<"u16", (ins shr_imm16:$imm), 0b01> {
3472 let Inst{21-20} = 0b01;
3501 def MVE_VSHL_immi16 : MVE_VSHL_imm<"i16", (ins imm0_15:$imm), 0b01> {
3502 let Inst{21-20} = 0b01;
3573 let Inst{11-10} = 0b01;
3889 "$Qd, $Qm, $imm6", vpred_r, "", !if(fsi, 0b10, 0b01), []> {
4013 defm n : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "n", 0b01>;
4100 let Inst{17-16} = 0b01;
4229 : MVE_VCMPqq<suffix, size, 0b11, pred_basic_fp, !if(size, 0b01, 0b10)> {
4254 def MVE_VCMPi16 : MVE_VCMPqqi<"i16", 0b01>;
4258 def MVE_VCMPu16 : MVE_VCMPqqu<"u16", 0b01>;
4262 def MVE_VCMPs16 : MVE_VCMPqqs<"s16", 0b01>;
4294 : MVE_VCMPqr<suffix, size, 0b11, pred_basic_fp, !if(size, 0b01, 0b10)> {
4319 def MVE_VCMPi16r : MVE_VCMPqri<"i16", 0b01>;
4323 def MVE_VCMPu16r : MVE_VCMPqru<"u16", 0b01>;
4327 def MVE_VCMPs16r : MVE_VCMPqrs<"s16", 0b01>;
4692 int_arm_mve_mull_int_predicated, 0b0, 0b01>;
4694 int_arm_mve_mull_int_predicated, 0b1, 0b01>;
4707 int_arm_mve_mull_int_predicated, 0b0, 0b01>;
4709 int_arm_mve_mull_int_predicated, 0b1, 0b01>;
4722 int_arm_mve_mull_poly_predicated, 0b0, 0b01>;
4724 int_arm_mve_mull_poly_predicated, 0b1, 0b01>;
4843 vpred_n, "$Qd = $Qd_src", !if(size, 0b10, 0b01), pattern> {
4865 defm MVE_VMOVNi32 : MVE_VxMOVxN_halves<"vmovn", "i32", 0b1, 0b0, 0b01>;
4867 defm MVE_VQMOVNs32 : MVE_VxMOVxN_halves<"vqmovn", "s32", 0b0, 0b1, 0b01>;
4869 defm MVE_VQMOVNu32 : MVE_VxMOVxN_halves<"vqmovn", "u32", 0b1, 0b1, 0b01>;
4871 defm MVE_VQMOVUNs32 : MVE_VxMOVxN_halves<"vqmovun", "s32", 0b0, 0b0, 0b01>;
5126 vpred_r, cstr, !if(size, 0b10, 0b01), pattern> {
5310 : MVE_qDest_rSrc<iname, suffix, cstr, !if(size, 0b10, 0b01), pattern> {
5499 def MVE_VBRSR16 : MVE_VBRSR<"vbrsr", "16", 0b01>;
5789 def MVE_VIDUPu16 : MVE_VxDUP<"vidup", "u16", 0b01, 0b0, v8i16, ARMvidup>;
5793 def MVE_VDDUPu16 : MVE_VxDUP<"vddup", "u16", 0b01, 0b1, v8i16, null_frag>;
5825 def MVE_VIWDUPu16 : MVE_VxWDUP<"viwdup", "u16", 0b01, 0b0>;
5829 def MVE_VDWDUPu16 : MVE_VxWDUP<"vdwdup", "u16", 0b01, 0b1>;
6059 MVE_vldst24_lanesize<16, 0b01>,
6160 def MVE_memH: MVE_memsz<0b01, 1, AddrModeT2_i7s2, "h", ["", "u", "s", "f"]>;
6306 defm MVE_VLDRBS16: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "s16", 0, 0b01>;
6308 defm MVE_VLDRBU16: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "u16", 1, 0b01>;
6317 defm MVE_VSTRB16: MVE_VLDRSTR_cw_m<MVE_st, MVE_memB, "vstrb", "16", 0, 0b01>;
6629 def MVE_VPTv8i16 : MVE_VPTt1i<"i16", 0b01>;
6640 def MVE_VPTv8u16 : MVE_VPTt1u<"u16", 0b01>;
6650 def MVE_VPTv8s16 : MVE_VPTt1s<"s16", 0b01>;
6673 def MVE_VPTv8i16r : MVE_VPTt2i<"i16", 0b01>;
6684 def MVE_VPTv8u16r : MVE_VPTt2u<"u16", 0b01>;
6694 def MVE_VPTv8s16r : MVE_VPTt2s<"s16", 0b01>;
6700 "", !if(size, 0b01, 0b10), pattern> {
6962 def MVE_DLSTP_16 : MVE_DLSTP<"dlstp.16", 0b01>;
6967 def MVE_WLSTP_16 : MVE_WLSTP<"wlstp.16", 0b01>;