Lines Matching refs:b01
3322 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3336 def v4f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3349 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3363 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3406 def v4i16 : N3VD_cmp<op24, op23, 0b01, op11_8, op4, itinD16,
3417 def v8i16 : N3VQ_cmp<op24, op23, 0b01, op11_8, op4, itinQ16,
3435 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3443 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3459 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3476 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3491 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3510 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3521 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3530 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3532 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3562 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3570 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3583 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3591 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3603 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3607 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3682 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3700 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3711 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3724 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3739 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3750 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3775 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3792 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3810 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3818 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3828 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3832 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3849 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3857 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3870 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD16,
3876 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ16,
3905 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3913 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3926 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3934 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3956 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3973 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3981 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3996 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
4004 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
4024 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4041 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4061 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4078 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4100 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4117 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4140 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4157 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4176 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4193 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4215 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4236 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4258 def VADDhd : N3VD<0, 0, 0b01, 0b1101, 0, IIC_VBIND, "vadd", "f16",
4261 def VADDhq : N3VQ<0, 0, 0b01, 0b1101, 0, IIC_VBINQ, "vadd", "f16",
4321 def VMULhd : N3VD<1, 0, 0b01, 0b1101, 1, IIC_VFMULD, "vmul", "f16",
4324 def VMULhq : N3VQ<1, 0, 0b01, 0b1101, 1, IIC_VFMULQ, "vmul", "f16",
4331 def VMULslhd : N3VDSL16<0b01, 0b1001, "vmul", "f16", v4f16, fmul>,
4333 def VMULslhq : N3VQSL16<0b01, 0b1001, "vmul", "f16", v8f16,
4464 def VMLAhd : N3VDMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACD, "vmla", "f16",
4467 def VMLAhq : N3VQMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACQ, "vmla", "f16",
4478 def VMLAslhd : N3VDMulOpSL16<0b01, 0b0001, IIC_VMACD, "vmla", "f16",
4481 def VMLAslhq : N3VQMulOpSL16<0b01, 0b0001, IIC_VMACQ, "vmla", "f16",
4680 def VMLSslhd : N3VDMulOpSL16<0b01, 0b0101, IIC_VMACD, "vmls", "f16",
4683 def VMLSslhq : N3VQMulOpSL16<0b01, 0b0101, IIC_VMACQ, "vmls", "f16",
4757 def VFMAhd : N3VDMulOp<0, 0, 0b01, 0b1100, 1, IIC_VFMACD, "vfma", "f16",
4761 def VFMAhq : N3VQMulOp<0, 0, 0b01, 0b1100, 1, IIC_VFMACQ, "vfma", "f16",
5125 def VCEQhd : N3VD_cmp<0,0,0b01,0b1110,0, IIC_VBIND, "vceq", "f16", v4i16, v4f16,
5128 def VCEQhq : N3VQ_cmp<0,0,0b01,0b1110,0, IIC_VBINQ, "vceq", "f16", v8i16, v8f16,
5133 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
5145 def VCGEhd : N3VD_cmp<1,0,0b01,0b1110,0, IIC_VBIND, "vcge", "f16", v4i16, v4f16,
5148 def VCGEhq : N3VQ_cmp<1,0,0b01,0b1110,0, IIC_VBINQ, "vcge", "f16", v8i16, v8f16,
5153 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
5155 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
5176 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
5178 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
5187 def VACGEhd : N3VDInt<1, 0, 0b01, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
5190 def VACGEhq : N3VQInt<1, 0, 0b01, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
5265 def VFMSLD : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>;
5267 def VFMSLQ : N3VCP8F16Q1<"vfmsl", QPR, DPR, DPR, 0b01, 0b10, 1>;
5269 def VFMSLDI : VFMD<"vfmsl", "f16", 0b01>;
5271 def VFMSLQI : VFMQ<"vfmsl", "f16", 0b01>;
5382 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5387 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5586 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5592 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5700 def VMAXhd : N3VDInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBIND,
5704 def VMAXhq : N3VQInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBINQ,
5719 def NEON_VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1,
5723 def NEON_VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1,
5777 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5786 def VPADDh : N3VDInt<1, 0, 0b01, 0b1101, 0, N3RegFrm,
5806 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5812 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5818 def VPMAXh : N3VDInt<1, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
5825 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5831 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5856 def VRECPEhd : N2VDInt<0b11, 0b11, 0b01, 0b11, 0b01010, 0,
5860 def VRECPEhq : N2VQInt<0b11, 0b11, 0b01, 0b11, 0b01010, 0,
5872 def VRECPShd : N3VDInt<0, 0, 0b01, 0b1111, 1, N3RegFrm,
5876 def VRECPShq : N3VQInt<0, 0, 0b01, 0b1111, 1, N3RegFrm,
5894 def VRSQRTEhd : N2VDInt<0b11, 0b11, 0b01, 0b11, 0b01011, 0,
5898 def VRSQRTEhq : N2VQInt<0b11, 0b11, 0b01, 0b11, 0b01011, 0,
6107 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
6109 def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
6112 def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
6115 def VABShd : N2VD<0b11, 0b11, 0b01, 0b01, 0b01110, 0,
6119 def VABShq : N2VQ<0b11, 0b11, 0b01, 0b01, 0b01110, 0,
6137 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
6141 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
6147 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
6150 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
6154 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
6158 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
6162 def VNEGhd : N2V<0b11, 0b11, 0b01, 0b01, 0b01111, 0, 0,
6167 def VNEGhq : N2V<0b11, 0b11, 0b01, 0b01, 0b01111, 1, 0,
6637 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
6641 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
6771 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
6801 def VCVTh2sd : N2VD<0b11, 0b11, 0b01, 0b11, 0b01110, 0, "vcvt", "s16.f16",
6804 def VCVTh2ud : N2VD<0b11, 0b11, 0b01, 0b11, 0b01111, 0, "vcvt", "u16.f16",
6807 def VCVTs2hd : N2VD<0b11, 0b11, 0b01, 0b11, 0b01100, 0, "vcvt", "f16.s16",
6810 def VCVTu2hd : N2VD<0b11, 0b11, 0b01, 0b11, 0b01101, 0, "vcvt", "f16.u16",
6814 def VCVTh2sq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01110, 0, "vcvt", "s16.f16",
6817 def VCVTh2uq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01111, 0, "vcvt", "u16.f16",
6820 def VCVTs2hq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01100, 0, "vcvt", "f16.s16",
6823 def VCVTu2hq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01101, 0, "vcvt", "f16.u16",
6839 def SDh : N2VDIntnp<0b01, 0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
6842 def SQh : N2VQIntnp<0b01, 0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
6845 def UDh : N2VDIntnp<0b01, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
6848 def UQh : N2VQIntnp<0b01, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
6940 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
6944 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
6968 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
6975 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
7001 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
7004 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
7126 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
7130 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
7136 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
7142 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
7148 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
7154 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
7279 def Dh : N2VDIntnp<0b01, 0b10, 0b100, 0, NoItinerary,
7285 def Qh : N2VQIntnp<0b01, 0b10, 0b100, 0, NoItinerary,
7342 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, null_frag>;
7347 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, null_frag>;
7350 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;
9250 def BF16_VCVT : N2V<0b11, 0b11, 0b01, 0b10, 0b01100, 1, 0,