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/llvm-project-15.0.7/llvm/test/MC/AVR/
H A Dinst-andi.s7 andi r16, 255
8 andi r29, 190
9 andi r22, 172
10 andi r27, 92
12 andi r20, BAR
14 ; CHECK: andi r16, 255 ; encoding: [0x0f,0x7f]
22 ; CHECK-INST: andi r16, 255
23 ; CHECK-INST: andi r29, 190
24 ; CHECK-INST: andi r22, 172
25 ; CHECK-INST: andi r27, 92
[all …]
H A Dinst-cbr.s12 ; CHECK: andi r17, -209 ; encoding: [0x1f,0x72]
13 ; CHECK: andi r24, -191 ; encoding: [0x81,0x74]
14 ; CHECK: andi r20, -174 ; encoding: [0x42,0x75]
15 ; CHECK: andi r31, -1 ; encoding: [0xff,0x7f]
17 ; CHECK-INST: andi r17, 47
18 ; CHECK-INST: andi r24, 65
19 ; CHECK-INST: andi r20, 82
20 ; CHECK-INST: andi r31, 255
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A DPR31345.ll7 ; CHECK: andi {{r[0-9]+}}, 0
8 ; CHECK-NOT: andi {{r[0-9]+}}, 255
15 ; CHECK: andi {{r[0-9]+}}, 179
16 ; CHECK-NOT: andi {{r[0-9]+}}, 255
23 ; CHECK-NOT: andi {{r[0-9]+}}, 255
24 ; CHECK: andi {{r[0-9]+}}, 0
31 ; CHECK-NOT: andi {{r[0-9]+}}, 255
32 ; CHECK: andi {{r[0-9]+}}, 179
39 ; CHECK-NOT: andi {{r[0-9]+}}, 255
47 ; CHECK: andi {{r[0-9]+}}, 205
[all …]
H A Dand.ll12 ; CHECK: andi r24, 5
27 ; CHECK: andi r24, 210
28 ; CHECK: andi r25, 4
45 ; CHECK: andi r22, 21
46 ; CHECK: andi r23, 205
47 ; CHECK: andi r24, 91
48 ; CHECK: andi r25, 7
73 ; CHECK: andi r21, 88
74 ; CHECK: andi r22, 76
75 ; CHECK: andi r23, 73
[all …]
H A Dctlz.ll23 ; CHECK: andi {{.*}}[[SCRATCH]], 15
28 ; CHECK: andi {{.*}}[[RESULT]], 85
31 ; CHECK: andi {{.*}}[[RESULT]], 51
34 ; CHECK: andi {{.*}}[[SCRATCH]], 51
39 ; CHECK: andi {{.*}}[[RESULT]], 15
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dand.ll409 ; MIPS-NEXT: andi $2, $4, 4
424 ; MIPS64-NEXT: andi $2, $4, 4
454 ; MIPS-NEXT: andi $2, $4, 4
499 ; MIPS-NEXT: andi $2, $4, 4
543 ; MIPS-NEXT: andi $3, $5, 4
593 ; MIPS-NEXT: andi $5, $7, 4
702 ; MIPS-NEXT: andi $2, $4, 31
747 ; MIPS-NEXT: andi $2, $4, 31
792 ; MIPS-NEXT: andi $2, $4, 31
836 ; MIPS-NEXT: andi $3, $5, 31
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/Fast-ISel/
H A Dbricmpi1.ll6 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
7 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
23 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
24 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
40 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
41 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
58 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
59 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
76 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
77 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dfunnel-shift-rot.ll23 ; CHECK-NEXT: andi $2, $4, 224
50 ; CHECK-NEXT: andi $1, $5, 15
53 ; CHECK-NEXT: andi $2, $2, 15
65 ; CHECK-NEXT: andi $1, $5, 31
68 ; CHECK-NEXT: andi $2, $2, 31
129 ; CHECK-NEXT: andi $8, $8, 31
130 ; CHECK-NEXT: andi $2, $2, 31
131 ; CHECK-NEXT: andi $3, $3, 31
132 ; CHECK-NEXT: andi $1, $1, 31
138 ; CHECK-NEXT: andi $2, $9, 31
[all …]
H A Dbittest.ll36 ; MIPS-NEXT: andi $1, $4, 1024
54 ; MIPS64-NEXT: andi $1, $4, 1024
76 ; MM32R3-NEXT: andi $1, $4, 1024
94 ; MIPS-NEXT: andi $1, $4, 32768
155 ; MIPS-NEXT: andi $2, $1, 1
173 ; MIPS64-NEXT: andi $1, $1, 1
270 ; MIPS-NEXT: andi $1, $5, 1024
398 ; MIPS-NEXT: andi $3, $1, 1
422 ; MIPS64-NEXT: andi $2, $1, 1
485 ; MIPS64-NEXT: andi $2, $1, 1
[all …]
H A Dsrem-seteq-illegal-types.ll52 ; MIPSEL-NEXT: andi $1, $1, 1
59 ; MIPSEL-NEXT: andi $1, $1, 15
74 ; MIPS64EL-NEXT: andi $2, $2, 1
80 ; MIPS64EL-NEXT: andi $1, $1, 15
95 ; MIPSEL-NEXT: andi $1, $1, 3
97 ; MIPSEL-NEXT: andi $1, $1, 60
99 ; MIPSEL-NEXT: andi $1, $1, 63
109 ; MIPS64EL-NEXT: andi $2, $2, 3
111 ; MIPS64EL-NEXT: andi $2, $2, 60
113 ; MIPS64EL-NEXT: andi $1, $1, 63
H A Dfcmp.ll50 ; 32-CMP-DAG: andi $2, $[[T1]], 1
54 ; 64-CMP-DAG: andi $2, $[[T1]], 1
83 ; 32-CMP-DAG: andi $2, $[[T1]], 1
87 ; 64-CMP-DAG: andi $2, $[[T1]], 1
116 ; 32-CMP-DAG: andi $2, $[[T1]], 1
120 ; 64-CMP-DAG: andi $2, $[[T1]], 1
149 ; 32-CMP-DAG: andi $2, $[[T1]], 1
153 ; 64-CMP-DAG: andi $2, $[[T1]], 1
182 ; 32-CMP-DAG: andi $2, $[[T1]], 1
186 ; 64-CMP-DAG: andi $2, $[[T1]], 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-masked-scatter.ll38 ; RV64ZVE32F-NEXT: andi a1, a1, 1
74 ; RV64ZVE32F-NEXT: andi a3, a2, 1
77 ; RV64ZVE32F-NEXT: andi a0, a2, 2
84 ; RV64ZVE32F-NEXT: andi a0, a2, 2
121 ; RV64ZVE32F-NEXT: andi a3, a2, 1
125 ; RV64ZVE32F-NEXT: andi a0, a2, 2
132 ; RV64ZVE32F-NEXT: andi a0, a2, 2
178 ; RV64ZVE32F-NEXT: andi a3, a2, 1
182 ; RV64ZVE32F-NEXT: andi a0, a2, 2
189 ; RV64ZVE32F-NEXT: andi a0, a2, 2
[all …]
H A Dfixed-vectors-masked-gather.ll41 ; RV64ZVE32F-NEXT: andi a1, a1, 1
80 ; RV64ZVE32F-NEXT: andi a3, a2, 1
83 ; RV64ZVE32F-NEXT: andi a0, a2, 2
91 ; RV64ZVE32F-NEXT: andi a0, a2, 2
133 ; RV64ZVE32F-NEXT: andi a3, a2, 1
140 ; RV64ZVE32F-NEXT: andi a0, a2, 2
187 ; RV64ZVE32F-NEXT: andi a3, a2, 1
194 ; RV64ZVE32F-NEXT: andi a0, a2, 2
241 ; RV64ZVE32F-NEXT: andi a3, a2, 1
248 ; RV64ZVE32F-NEXT: andi a0, a2, 2
[all …]
H A Dfixed-vectors-unaligned.ll54 ; RV32-NEXT: andi a1, a0, 1
57 ; RV32-NEXT: andi a0, a0, 2
71 ; RV32-NEXT: andi a0, a0, 2
91 ; RV64-NEXT: andi a1, a0, 1
94 ; RV64-NEXT: andi a0, a0, 2
108 ; RV64-NEXT: andi a0, a0, 2
134 ; RV32-NEXT: andi a1, a0, 1
139 ; RV32-NEXT: andi a0, a0, 2
152 ; RV32-NEXT: andi a0, a0, 2
172 ; RV64-NEXT: andi a1, a0, 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dselect_const.ll192 ; ISEL-NEXT: andi. 3, 3, 1
215 ; ISEL-NEXT: andi. 3, 3, 1
238 ; ISEL-NEXT: andi. 3, 3, 1
263 ; ISEL-NEXT: andi. 3, 3, 1
287 ; ISEL-NEXT: andi. 3, 3, 1
311 ; ISEL-NEXT: andi. 3, 3, 1
335 ; ISEL-NEXT: andi. 3, 3, 1
359 ; ISEL-NEXT: andi. 3, 3, 1
381 ; ISEL-NEXT: andi. 3, 3, 1
403 ; ISEL-NEXT: andi. 3, 3, 1
[all …]
H A Dpopcnt-zext.ll18 ; SLOW-NEXT: andi. 3, 3, 85
20 ; SLOW-NEXT: andi. 4, 3, 13107
22 ; SLOW-NEXT: andi. 3, 3, 13107
45 ; SLOW-NEXT: andi. 4, 4, 85
49 ; SLOW-NEXT: andi. 3, 3, 51
71 ; SLOW-NEXT: andi. 3, 3, 85
78 ; SLOW-NEXT: andi. 5, 5, 13107
106 ; SLOW-NEXT: andi. 4, 4, 85
110 ; SLOW-NEXT: andi. 3, 3, 51
132 ; SLOW-NEXT: andi. 3, 3, 21845
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/ir-instruction/
H A Dsext-zext-trunc.ll9 ; LA32-NEXT: andi $a0, $a0, 1
15 ; LA64-NEXT: andi $a0, $a0, 1
25 ; LA32-NEXT: andi $a0, $a0, 1
31 ; LA64-NEXT: andi $a0, $a0, 1
41 ; LA32-NEXT: andi $a0, $a0, 1
47 ; LA64-NEXT: andi $a0, $a0, 1
57 ; LA32-NEXT: andi $a0, $a0, 1
64 ; LA64-NEXT: andi $a0, $a0, 1
160 ; LA32-NEXT: andi $a0, $a0, 1
165 ; LA64-NEXT: andi $a0, $a0, 1
[all …]
H A Dselect-bare-int.ll9 ; LA32-NEXT: andi $a0, $a0, 1
17 ; LA64-NEXT: andi $a0, $a0, 1
29 ; LA32-NEXT: andi $a0, $a0, 1
37 ; LA64-NEXT: andi $a0, $a0, 1
49 ; LA32-NEXT: andi $a0, $a0, 1
57 ; LA64-NEXT: andi $a0, $a0, 1
69 ; LA32-NEXT: andi $a0, $a0, 1
77 ; LA64-NEXT: andi $a0, $a0, 1
89 ; LA32-NEXT: andi $a5, $a0, 1
100 ; LA64-NEXT: andi $a0, $a0, 1
H A Dand.ll113 ; LA32-NEXT: andi $a0, $a0, 5
118 ; LA64-NEXT: andi $a0, $a0, 5
128 ; LA32-NEXT: andi $a0, $a0, 1
133 ; LA64-NEXT: andi $a0, $a0, 1
143 ; LA32-NEXT: andi $a0, $a0, 5
148 ; LA64-NEXT: andi $a0, $a0, 5
175 ; LA32-NEXT: andi $a0, $a0, 1
180 ; LA64-NEXT: andi $a0, $a0, 1
190 ; LA32-NEXT: andi $a0, $a0, 5
195 ; LA64-NEXT: andi $a0, $a0, 5
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Arithmetic/
H A Dint-range-interface.mlir28 %5 = arith.andi %3, %4 : i1
45 %5 = arith.andi %3, %4 : i1
83 %5 = arith.andi %3, %4 : i1
154 %7 = arith.andi %3, %4 : i1
155 %8 = arith.andi %7, %5 : i1
156 %9 = arith.andi %8, %6 : i1
175 %7 = arith.andi %3, %4 : i1
176 %8 = arith.andi %7, %5 : i1
210 %7 = arith.andi %3, %6 : i1
230 %6 = arith.andi %3, %5 : i1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dsext-zext-trunc.ll10 ; RV32I-NEXT: andi a0, a0, 1
16 ; RV64I-NEXT: andi a0, a0, 1
26 ; RV32I-NEXT: andi a0, a0, 1
32 ; RV64I-NEXT: andi a0, a0, 1
42 ; RV32I-NEXT: andi a0, a0, 1
48 ; RV64I-NEXT: andi a0, a0, 1
58 ; RV32I-NEXT: andi a0, a0, 1
65 ; RV64I-NEXT: andi a0, a0, 1
171 ; RV32I-NEXT: andi a0, a0, 1
176 ; RV64I-NEXT: andi a0, a0, 1
[all …]
H A Durem-seteq-illegal-types.ll197 ; RV32-NEXT: andi a0, a0, 15
207 ; RV64-NEXT: andi a0, a0, 15
217 ; RV32M-NEXT: andi a0, a0, 15
227 ; RV64M-NEXT: andi a0, a0, 15
237 ; RV32MV-NEXT: andi a0, a0, 15
247 ; RV64MV-NEXT: andi a0, a0, 15
263 ; RV32-NEXT: andi a0, a0, 511
276 ; RV64-NEXT: andi a0, a0, 511
287 ; RV32M-NEXT: andi a0, a0, 511
296 ; RV64M-NEXT: andi a0, a0, 511
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dmul.ll31 ; MIPS32-NEXT: andi $2, $1, 255
67 ; MIPS32-NEXT: andi $2, $1, 65535
126 ; MIPS32-NEXT: andi $4, $4, 1
129 ; MIPS32-NEXT: andi $5, $5, 1
140 ; MIPS32-NEXT: andi $5, $5, 1
143 ; MIPS32-NEXT: andi $24, $24, 1
147 ; MIPS32-NEXT: andi $15, $15, 1
151 ; MIPS32-NEXT: andi $11, $11, 1
155 ; MIPS32-NEXT: andi $10, $10, 1
189 ; MIPS32-NEXT: andi $2, $2, 1
[all …]
H A Dselect.ll8 ; MIPS32-NEXT: andi $1, $4, 1
21 ; MIPS32-NEXT: andi $1, $4, 1
34 ; MIPS32-NEXT: andi $1, $4, 1
47 ; MIPS32-NEXT: andi $1, $4, 1
62 ; MIPS32-NEXT: andi $1, $1, 1
80 ; MIPS32-NEXT: andi $1, $4, 1
95 ; MIPS32-NEXT: andi $1, $4, 1
111 ; MIPS32-NEXT: andi $1, $4, 1
127 ; MIPS32-NEXT: andi $3, $4, 1
146 ; MIPS32-NEXT: andi $1, $1, 1
H A Dbswap.ll12 ; MIPS32-NEXT: andi $2, $4, 65280
16 ; MIPS32-NEXT: andi $2, $2, 65280
39 ; MIPS32-NEXT: andi $2, $5, 65280
43 ; MIPS32-NEXT: andi $2, $2, 65280
48 ; MIPS32-NEXT: andi $3, $4, 65280
52 ; MIPS32-NEXT: andi $3, $3, 65280

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