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Searched refs:addUse (Results 1 – 25 of 50) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp404 .addUse(SrcReg) in selectUnOpWithSrc()
528 .addUse(Ptr) in selectAtomicRMW()
586 .addUse(Ptr) in selectAtomicCmpXchg()
590 .addUse(Val) in selectAtomicCmpXchg()
833 .addUse(Cmp0) in selectCmp()
834 .addUse(Cmp1) in selectCmp()
940 .addUse(OneReg) in selectSelect()
989 .addUse(IntReg) in selectIntToBool()
990 .addUse(One) in selectIntToBool()
996 .addUse(Zero) in selectIntToBool()
[all …]
H A DSPIRVGlobalRegistry.cpp112 .addUse(getSPIRVTypeID(ElemType)) in getOpTypeVector()
163 .addUse(getSPIRVTypeID(SpvType)); in getOrCreateConstInt()
168 .addUse(getSPIRVTypeID(SpvType)); in getOrCreateConstInt()
282 MIB.addUse(SpvScalConst); in getOrCreateConsIntVector()
332 MIB.addUse(Init->getOperand(0).getReg()); in buildGlobalVariable()
386 .addUse(NumElementsVReg); in getOpTypeArray()
414 MIB.addUse(Ty); in getOpTypeStruct()
451 .addUse(getSPIRVTypeID(ElemType)); in getOpTypePointer()
458 .addUse(createTypeVReg(MIRBuilder)) in getOpTypeForwardPointer()
469 MIB.addUse(getSPIRVTypeID(ArgType)); in getOpTypeFunction()
[all …]
H A DSPIRVCallLowering.cpp41 .addUse(VRegs[0]) in lowerReturn()
224 .addUse(GR->getSPIRVTypeID(RetTy)) in lowerFormalArguments()
226 .addUse(GR->getSPIRVTypeID(FuncTy)); in lowerFormalArguments()
235 .addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i])); in lowerFormalArguments()
248 .addUse(FuncVReg); in lowerFormalArguments()
316 .addUse(GR->getSPIRVTypeID(RetType)) in lowerCall()
323 MIB.addUse(Arg.Regs[0]); in lowerCall()
H A DSPIRVUtils.cpp102 auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target); in buildOpName()
120 .addUse(Reg) in buildOpDecorate()
130 .addUse(Reg) in buildOpDecorate()
H A DSPIRVPreLegalizer.cpp213 .addUse(NewReg) in insertAssignInstr()
214 .addUse(GR->getSPIRVTypeID(SpirvTy)); in insertAssignInstr()
341 MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg()); in processInstr()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp279 .addUse(TiedDest) in buildUnalignedLoad()
334 .addUse(PseudoMULTuReg); in select()
363 .addUse(Mips::ZERO) in select()
385 .addUse(JTIndex); in select()
393 .addUse(DestAddress) in select()
414 .addUse(Dest); in select()
528 .addUse(HILOReg); in select()
714 .addUse(LUiReg) in select()
812 MIB.addUse(Instruction.RHS); in select()
874 .addUse(Mips::ZERO) in select()
[all …]
H A DMipsISelLowering.cpp4849 .addUse(Hi) in emitLDR_D()
4919 .addUse(Tmp) in emitSTR_W()
4931 .addUse(Tmp) in emitSTR_W()
4935 .addUse(Tmp) in emitSTR_W()
4972 .addUse(Lo) in emitSTR_D()
4991 .addUse(Lo) in emitSTR_D()
4995 .addUse(Hi) in emitSTR_D()
5015 .addUse(Lo) in emitSTR_D()
5019 .addUse(Lo) in emitSTR_D()
5023 .addUse(Hi) in emitSTR_D()
[all …]
H A DMipsSEISelDAGToDAG.cpp135 .addUse(Mips::RA_64, RegState::Undef) in emitMCountABI()
136 .addUse(Mips::ZERO_64); in emitMCountABI()
138 MIB.addUse(Mips::AT_64, RegState::Implicit); in emitMCountABI()
143 .addUse(Mips::RA, RegState::Undef) in emitMCountABI()
144 .addUse(Mips::ZERO); in emitMCountABI()
148 .addUse(Mips::SP) in emitMCountABI()
151 MIB.addUse(Mips::AT, RegState::Implicit); in emitMCountABI()
H A DMipsCallLowering.cpp224 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
487 MIB.addUse(CalleeReg); in lowerCall()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp233 .addUse(MisspeculatingTaintReg) in insertTrackingCode()
234 .addUse(AArch64::XZR) in insertTrackingCode()
371 .addUse(AArch64::SP) in insertSPToRegTaintPropagation()
377 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
378 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
394 .addUse(AArch64::SP) in insertRegToSPTaintPropagation()
401 .addUse(MisspeculatingTaintReg, RegState::Kill) in insertRegToSPTaintPropagation()
406 .addUse(TmpReg, RegState::Kill) in insertRegToSPTaintPropagation()
454 .addUse(Reg); in makeGPRSpeculationSafe()
578 .addUse(SrcReg, RegState::Kill) in expandSpeculationSafeValue()
[all …]
H A DAArch64ExpandPseudoInsts.cpp330 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
331 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
804 .addUse(CtxReg) in expandStoreSwiftAsyncContext()
805 .addUse(BaseReg) in expandStoreSwiftAsyncContext()
821 .addUse(BaseReg) in expandStoreSwiftAsyncContext()
826 .addUse(AArch64::X16) in expandStoreSwiftAsyncContext()
833 .addUse(AArch64::XZR) in expandStoreSwiftAsyncContext()
834 .addUse(CtxReg) in expandStoreSwiftAsyncContext()
838 .addUse(AArch64::X17) in expandStoreSwiftAsyncContext()
843 .addUse(BaseReg) in expandStoreSwiftAsyncContext()
[all …]
H A DAArch64LowerHomogeneousPrologEpilog.cpp314 .addUse(AArch64::SP) in getOrCreateFrameHelper()
330 .addUse(AArch64::LR) in getOrCreateFrameHelper()
558 .addUse(AArch64::SP) in lowerProlog()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2131 .addUse(Hi) in extractF64Exponent()
3789 .addUse(RHS) in legalizeFastUnsafeFDIV()
3817 .addUse(Y) in legalizeFastUnsafeFDIV64()
3861 .addUse(RHS) in legalizeFDIV16()
3862 .addUse(LHS) in legalizeFDIV16()
3960 .addUse(RHS) in legalizeFDIV32()
3961 .addUse(LHS) in legalizeFDIV32()
3986 .addUse(LHS) in legalizeFDIV64()
3987 .addUse(RHS) in legalizeFDIV64()
4002 .addUse(LHS) in legalizeFDIV64()
[all …]
H A DAMDGPUPostLegalizerCombiner.cpp233 .addUse(SqrtSrcMI->getOperand(0).getReg()) in matchRcpSqrtToRsq()
243 .addUse(RcpSrcMI->getOperand(0).getReg()) in matchRcpSqrtToRsq()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp581 .addUse(LHSReg) in insertComparison()
582 .addUse(RHSReg) in insertComparison()
600 .addUse(PrevRes) in insertComparison()
778 .addUse(CondReg) in selectSelect()
794 .addUse(TrueReg) in selectSelect()
795 .addUse(FalseReg) in selectSelect()
888 .addUse(AndResult) in select()
938 .addUse(SrcReg) in select()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp653 RegSequence.addUse(Regs[I]); in createTuple()
969 .addUse(SrcReg) in selectCopy()
1824 Shl.addUse(Src2Reg); in selectVectorSHL()
1912 .addUse(ListReg) in selectVaStartDarwin()
2861 .addUse(NewDst) in select()
2934 .addUse(LdReg) in select()
3178 .addUse(SrcReg) in select()
4270 .addUse(SrcReg) in selectUnmergeValues()
4296 .addUse(InsReg) in selectUnmergeValues()
4642 CmpMI.addUse(RHS); in emitFPCompare()
[all …]
H A DAArch64LegalizerInfo.cpp1109 NewI.addUse(Base); in legalizeLoadStore()
1279 .addUse(HSum); in legalizeCTPOP()
1336 .addUse(DesiredI->getOperand(0).getReg()) in legalizeAtomicCmpxchg128()
1338 .addUse(DesiredI->getOperand(1).getReg()) in legalizeAtomicCmpxchg128()
1341 .addUse(NewI->getOperand(0).getReg()) in legalizeAtomicCmpxchg128()
1343 .addUse(NewI->getOperand(1).getReg()) in legalizeAtomicCmpxchg128()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp264 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
273 .addUse(TablePtr) in buildBrJT()
275 .addUse(IndexReg); in buildBrJT()
819 .addUse(Addr) in buildAtomicCmpXchgWithSuccess()
820 .addUse(CmpVal) in buildAtomicCmpXchgWithSuccess()
821 .addUse(NewVal) in buildAtomicCmpXchgWithSuccess()
844 .addUse(Addr) in buildAtomicCmpXchg()
845 .addUse(CmpVal) in buildAtomicCmpXchg()
846 .addUse(NewVal) in buildAtomicCmpXchg()
H A DRegBankSelect.cpp165 .addUse(Src); in repairReg()
197 MergeBuilder.addUse(SrcReg); in repairReg()
206 UnMergeBuilder.addUse(MO.getReg()); in repairReg()
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DCSETest.cpp96 .addUse(Copies[0]) in TEST_F()
97 .addUse(Copies[1]); in TEST_F()
H A DMachineIRBuilderTest.cpp169 .addUse(Copies[0]); in TEST_F()
175 .addUse(Copies[1]); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp793 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); in expandPseudoLogM()
794 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); in expandPseudoLogM()
798 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); in expandPseudoLogM()
799 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); in expandPseudoLogM()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallLowering.cpp109 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
347 MIB.addUse(X86::AL, RegState::Implicit); in lowerCall()
H A DX86FrameLowering.cpp1527 .addUse(MachineFramePtr) in emitPrologue()
1528 .addUse(X86::RIP) in emitPrologue()
1530 .addUse(X86::NoRegister) in emitPrologue()
1533 .addUse(X86::NoRegister); in emitPrologue()
1540 .addUse(MachineFramePtr) in emitPrologue()
1697 .addUse(X86::RSP) in emitPrologue()
1699 .addUse(X86::NoRegister) in emitPrologue()
1701 .addUse(X86::NoRegister) in emitPrologue()
1704 .addUse(X86::RSP) in emitPrologue()
2233 .addUse(MachineFramePtr) in emitEpilogue()
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DValue.h505 void addUse(Use &U) { U.addToList(&UseList); } in addUse() function
871 if (V) V->addUse(*this); in set()

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