Lines Matching refs:addUse

653     RegSequence.addUse(Regs[I]);  in createTuple()
969 .addUse(SrcReg) in selectCopy()
1824 Shl.addUse(Src2Reg); in selectVectorSHL()
1911 .addUse(ArgsAddrReg) in selectVaStartDarwin()
1912 .addUse(ListReg) in selectVaStartDarwin()
1939 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
2648 .addUse(SrcReg, 0, Offset == 0 ? AArch64::sube64 : AArch64::subo64); in select()
2711 .addUse(I.getOperand(2).getReg()) in select()
2861 .addUse(NewDst) in select()
2890 IsStore ? NewInst.addUse(CurValReg) : NewInst.addDef(CurValReg); in select()
2934 .addUse(LdReg) in select()
3178 .addUse(SrcReg) in select()
3254 .addUse(SubregToRegSrc) in select()
3286 .addUse(SrcReg) in select()
3653 .addUse(AArch64::X0, RegState::Implicit) in selectTLSGlobalValue()
4017 .addUse(I.getOperand(1).getReg()) in selectMergeValues()
4025 .addUse(I.getOperand(2).getReg()) in selectMergeValues()
4030 .addUse(SubToRegDef) in selectMergeValues()
4031 .addUse(SubToRegDef2) in selectMergeValues()
4269 .addUse(ImpDefReg) in selectUnmergeValues()
4270 .addUse(SrcReg) in selectUnmergeValues()
4296 .addUse(InsReg) in selectUnmergeValues()
4639 auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addUse(LHS); in emitFPCompare()
4642 CmpMI.addUse(RHS); in emitFPCompare()
4701 .addUse(WidenedOp2->getOperand(0).getReg()) in emitVectorConcat()
5225 .addUse(InsSub->getOperand(0).getReg()) in emitLaneInsert()
5230 .addUse(EltReg); in emitLaneInsert()
5291 .addUse(NewReg) in selectUSMovFromExtend()
5479 .addUse(EltReg) in tryOptBuildVecToSubregToReg()
5810 PAC.addUse(DiscReg); in selectIntrinsic()
6133 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(Base.getReg()); }, in selectExtendedSHL()
6134 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); }, in selectExtendedSHL()
6210 MIB.addUse(Gep->getOperand(1).getReg()); in selectAddrModeRegisterOffset()
6213 MIB.addUse(Gep->getOperand(2).getReg()); in selectAddrModeRegisterOffset()
6353 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(LHS.getReg()); }, in selectAddrModeWRO()
6354 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
6431 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(AdrpReg); }, in tryFoldAddLowIntoImm()
6553 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ShiftReg); }, in selectShiftedRegister()
6694 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectArithExtendedRegister()