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Searched refs:addDef (Results 1 – 25 of 55) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp276 .addDef(Dest) in buildUnalignedLoad()
326 .addDef(PseudoMULTuReg) in select()
375 .addDef(JTIndex) in select()
392 .addDef(Dest) in select()
404 .addDef(Dest) in select()
482 .addDef(ImplDef); in select()
519 .addDef(HILOReg) in select()
577 .addDef(Dst); in select()
652 .addDef(ResultInFPR) in select()
873 .addDef(TrueInReg) in select()
[all …]
H A DMipsISelLowering.cpp4783 .addDef(Temp) in emitLDR_W()
4830 .addDef(Temp) in emitLDR_D()
4839 .addDef(Lo) in emitLDR_D()
4843 .addDef(Hi) in emitLDR_D()
4915 .addDef(Tmp) in emitSTR_W()
4927 .addDef(Tmp) in emitSTR_W()
4968 .addDef(Lo) in emitSTR_D()
4983 .addDef(Lo) in emitSTR_D()
4987 .addDef(Hi) in emitSTR_D()
5007 .addDef(Lo) in emitSTR_D()
[all …]
H A DMipsCallLowering.cpp122 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
479 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
540 MIB.addDef(Mips::GP, RegState::Implicit); in lowerCall()
H A DMipsSEISelDAGToDAG.cpp134 .addDef(Mips::AT_64) in emitMCountABI()
142 .addDef(Mips::AT) in emitMCountABI()
147 .addDef(Mips::SP) in emitMCountABI()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.cpp76 .addDef(createTypeVReg(MIRBuilder)); in getOpTypeBool()
99 .addDef(createTypeVReg(MIRBuilder)); in getOpTypeVoid()
162 .addDef(Res) in getOrCreateConstInt()
167 .addDef(Res) in getOrCreateConstInt()
204 .addDef(Res) in buildConstantInt()
210 .addDef(Res) in buildConstantInt()
279 .addDef(SpvVecConst) in getOrCreateConsIntVector()
285 .addDef(SpvVecConst) in getOrCreateConsIntVector()
327 .addDef(ResVReg) in buildGlobalVariable()
449 .addDef(Reg) in getOpTypePointer()
[all …]
H A DSPIRVInstructionSelector.cpp402 .addDef(ResVReg) in selectUnOpWithSrc()
526 .addDef(ResVReg) in selectAtomicRMW()
786 .addDef(ResVReg) in selectBitreverse()
831 .addDef(ResVReg) in selectCmp()
937 .addDef(ResVReg) in selectSelect()
987 .addDef(BitIntReg) in selectIntToBool()
993 .addDef(ResVReg) in selectIntToBool()
1048 .addDef(ResVReg) in selectOpUndef()
1106 .addDef(ResVReg) in selectInsertElt()
1121 .addDef(ResVReg) in selectExtractElt()
[all …]
H A DSPIRVCallLowering.cpp223 .addDef(FuncVReg) in lowerFormalArguments()
234 .addDef(VRegs[i][0]) in lowerFormalArguments()
315 .addDef(ResVReg) in lowerCall()
H A DSPIRVPreLegalizer.cpp212 .addDef(Reg) in insertAssignInstr()
341 MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg()); in processInstr()
H A DSPIRVLegalizerInfo.cpp269 .addDef(ConvReg) in convertPtrToInt()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp232 .addDef(MisspeculatingTaintReg) in insertTrackingCode()
370 .addDef(AArch64::XZR) in insertSPToRegTaintPropagation()
376 .addDef(MisspeculatingTaintReg) in insertSPToRegTaintPropagation()
393 .addDef(TmpReg) in insertRegToSPTaintPropagation()
399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
405 .addDef(AArch64::SP) in insertRegToSPTaintPropagation()
453 .addDef(Reg) in makeGPRSpeculationSafe()
577 .addDef(DstReg) in expandSpeculationSafeValue()
H A DAArch64LowerHomogeneousPrologEpilog.cpp211 MIB.addDef(AArch64::SP); in emitStore()
234 MIB.addDef(AArch64::SP); in emitLoad()
313 .addDef(AArch64::FP) in getOrCreateFrameHelper()
328 .addDef(AArch64::X16) in getOrCreateFrameHelper()
557 .addDef(AArch64::FP) in lowerProlog()
H A DAArch64ExpandPseudoInsts.cpp652 .addDef(AddressReg) in expandSetTagLoop()
659 .addDef(SizeReg) in expandSetTagLoop()
1029 .addDef(Reg32) in expandMI()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp793 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); in expandPseudoLogM()
794 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); in expandPseudoLogM()
798 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); in expandPseudoLogM()
799 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); in expandPseudoLogM()
928 .addDef(VMX) in expandPostRAPseudo()
934 .addDef(VMX) in expandPostRAPseudo()
942 .addDef(VMX) in expandPostRAPseudo()
951 .addDef(VMX) in expandPostRAPseudo()
1102 .addDef(MI.getOperand(0).getReg()) in expandGetStackTopPseudo()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp495 .addDef(DestReg) in putConstant()
599 .addDef(ResReg) in insertComparison()
696 .addDef(ResultReg) in selectGlobal()
793 .addDef(ResReg) in selectSelect()
887 .addDef(SExtResult) in select()
936 .addDef(DstReg) in select()
937 .addDef(IgnoredBits) in select()
H A DARMLowOverheadLoops.cpp1478 MIB.addDef(ARM::LR); in RevertLoopEndDec()
1563 MIB.addDef(ARM::LR); in ExpandLoopStart()
1723 MIB.addDef(ARM::LR); in Expand()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp292 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildConstant()
325 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildFConstant()
733 MIB.addDef(ResultReg); in buildIntrinsic()
817 .addDef(OldValRes) in buildAtomicCmpXchgWithSuccess()
818 .addDef(SuccessRes) in buildAtomicCmpXchgWithSuccess()
843 .addDef(OldValRes) in buildAtomicCmpXchg()
984 return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); in buildBlockAddress()
H A DRegBankSelect.cpp164 .addDef(Dst) in repairReg()
194 .addDef(MO.getReg()); in repairReg()
204 UnMergeBuilder.addDef(DefReg); in repairReg()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallLowering.cpp228 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
345 .addDef(X86::AL) in lowerCall()
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DCSETest.cpp95 .addDef(MRI->createGenericVirtualRegister(s32)) in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp165 MIB.addDef(PhysReg, RegState::Implicit); in assignValueToReg()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp656 .addDef(LoLHS) in split64BitValueForMapping()
657 .addDef(HiLHS) in split64BitValueForMapping()
790 .addDef(InitSaveExecReg); in executeInWaterfallLoop()
822 .addDef(PhiExec) in executeInWaterfallLoop()
931 .addDef(NewExec) in executeInWaterfallLoop()
940 .addDef(ExecReg) in executeInWaterfallLoop()
957 .addDef(ExecReg) in executeInWaterfallLoop()
1852 .addDef(DstReg) in buildVCopy()
1862 .addDef(TmpReg0) in buildVCopy()
1865 .addDef(TmpReg1) in buildVCopy()
[all …]
H A DAMDGPUInstructionSelector.cpp342 .addDef(UnusedCarry, RegState::Dead) in selectG_ADD_SUB()
376 .addDef(CarryReg) in selectG_ADD_SUB()
940 .addDef(Dst1) in selectDivScale()
1717 MIB.addDef(TmpReg); in selectImageIntrinsic()
1724 MIB.addDef(VDataOut); // vdata output in selectImageIntrinsic()
4568 .addDef(RSrc2) in buildRSRC()
4571 .addDef(RSrc3) in buildRSRC()
4578 .addDef(RSrcHi) in buildRSRC()
4588 .addDef(RSrcLo) in buildRSRC()
4593 .addDef(RSrc) in buildRSRC()
[all …]
H A DSIShrinkInstructions.cpp679 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
680 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp799 .addDef(Hexagon::D15) in insertEpilogueInBlock()
849 .addDef(Hexagon::D15) in insertEpilogueInBlock()
855 .addDef(Hexagon::D15) in insertEpilogueInBlock()
876 .addDef(Hexagon::D15) in insertEpilogueInBlock()
907 .addDef(SP) in insertAllocframe()
919 .addDef(SP) in insertAllocframe()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h83 MIB.addDef(Reg); in addDefToMIB()
86 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy)); in addDefToMIB()
89 MIB.addDef(MRI.createVirtualRegister(RC)); in addDefToMIB()

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