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/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dstore.ll12 ; CHECK: st {{[YZ]}}, r22
13 ; CHECK: std {{[YZ]}}+1, r23
20 ; CHECK: std {{[YZ]}}+63, r22
39 ; CHECK: std {{[YZ]}}+62, r22
40 ; CHECK: std {{[YZ]}}+63, r23
51 ; CHECK: st {{[YZ]}}, r22
52 ; CHECK: std {{[YZ]}}+1, r23
H A Dload.ll12 ; CHECK: ld r24, [[PTR:[YZ]]]
20 ; CHECK: ldd r24, {{[YZ]}}+63
39 ; CHECK: ldd r24, [[PTR:[YZ]]]+62
51 ; CHECK: ld r24, [[PTR:[YZ]]]
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dcondprop.ll11 ; CHECK-NEXT: [[YZ:%.*]] = icmp eq i32 [[Y:%.*]], 0
12 ; CHECK-NEXT: [[Z:%.*]] = and i1 [[XZ]], [[YZ]]
42 ; CHECK-NEXT: [[YZ:%.*]] = icmp eq i32 [[Y:%.*]], 0
43 ; CHECK-NEXT: [[Z:%.*]] = select i1 [[XZ]], i1 [[YZ]], i1 false
73 ; CHECK-NEXT: [[YZ:%.*]] = icmp ne i32 [[Y:%.*]], 0
74 ; CHECK-NEXT: [[Z:%.*]] = or i1 [[XZ]], [[YZ]]
104 ; CHECK-NEXT: [[YZ:%.*]] = icmp ne i32 [[Y:%.*]], 0
105 ; CHECK-NEXT: [[Z:%.*]] = select i1 [[XZ]], i1 true, i1 [[YZ]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dshould-change-type.ll47 ; CHECK-NEXT: [[YZ:%.*]] = zext i9 [[Y:%.*]] to i64
48 ; CHECK-NEXT: [[C:%.*]] = add nuw nsw i64 [[XZ]], [[YZ]]
/llvm-project-15.0.7/llvm/test/Transforms/Util/PredicateInfo/
H A Dtestandor.ll11 ; CHECK-NEXT: [[YZ:%.*]] = icmp eq i32 [[Y:%.*]], 0
12 ; CHECK-NEXT: [[Z:%.*]] = or i1 [[XZ]], [[YZ]]
21 ; CHECK-NEXT: call void @foo(i1 [[YZ]])
56 ; CHECK-NEXT: [[YZ:%.*]] = icmp eq i32 [[Y:%.*]], 0
66 ; CHECK-NEXT: call void @foo(i1 [[YZ]])
102 ; CHECK-NEXT: [[Z:%.*]] = and i1 [[XZ]], [[YZ]]
117 ; CHECK-NEXT: call void @foo(i1 [[YZ]])
162 ; CHECK-NEXT: call void @foo(i1 [[YZ]])
230 ; CHECK-NEXT: [[Z:%.*]] = and i1 [[XZ]], [[YZ]]
275 ; CHECK-NEXT: [[Z:%.*]] = or i1 [[XZ]], [[YZ]]
[all …]
H A Dcondprop.ll99 ; CHECK-NEXT: [[YZ:%.*]] = icmp eq i32 [[Y:%.*]], 0
100 ; CHECK-NEXT: [[Z:%.*]] = and i1 [[XZ]], [[YZ]]
104 ; CHECK: [[YZ_0:%.*]] = call i1 @llvm.ssa.copy.{{.+}}(i1 [[YZ]])
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A Dcondprop.ll91 ; CHECK-NEXT: [[YZ:%.*]] = icmp eq i32 [[Y:%.*]], 0
92 ; CHECK-NEXT: [[Z:%.*]] = and i1 [[XZ]], [[YZ]]
122 ; CHECK-NEXT: [[YZ:%.*]] = icmp eq i32 [[Y:%.*]], 0
123 ; CHECK-NEXT: [[Z:%.*]] = select i1 [[XZ]], i1 [[YZ]], i1 false
153 ; CHECK-NEXT: [[YZ:%.*]] = icmp ne i32 [[Y:%.*]], 0
154 ; CHECK-NEXT: [[Z:%.*]] = or i1 [[XZ]], [[YZ]]
184 ; CHECK-NEXT: [[YZ:%.*]] = icmp ne i32 [[Y:%.*]], 0
185 ; CHECK-NEXT: [[Z:%.*]] = select i1 [[XZ]], i1 true, i1 [[YZ]]
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp603 auto *YZ = Builder.CreateFAddFMF(Y, Z, &I); in visitFMul() local
604 auto *NewPow = Builder.CreateBinaryIntrinsic(Intrinsic::pow, X, YZ, &I); in visitFMul()
612 auto *YZ = Builder.CreateAdd(Y, Z); in visitFMul() local
614 Intrinsic::powi, {X->getType(), YZ->getType()}, {X, YZ}, &I); in visitFMul()
1370 Value *YZ = Builder.CreateFMulFMF(Y, Op1, &I); in visitFDiv() local
1371 return BinaryOperator::CreateFDivFMF(X, YZ, &I); in visitFDiv()
1376 Value *YZ = Builder.CreateFMulFMF(Y, Op0, &I); in visitFDiv() local
1377 return BinaryOperator::CreateFDivFMF(YZ, X, &I); in visitFDiv()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp14240 auto tryToFoldXSubYZ = [&](SDValue X, SDValue YZ) { in visitFSUBForFMACombine() argument
14241 if (isContractableFMUL(YZ) && (Aggressive || YZ->hasOneUse())) { in visitFSUBForFMACombine()
14243 DAG.getNode(ISD::FNEG, SL, VT, YZ.getOperand(0)), in visitFSUBForFMACombine()
14244 YZ.getOperand(1), X); in visitFSUBForFMACombine()