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Searched refs:XVT (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h783 bool shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
786 if (XVT.isVector()) in shouldTransformSignedTruncationCheck()
797 return VTIsOk(XVT) && VTIsOk(KeptBitsVT); in shouldTransformSignedTruncationCheck()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h1079 shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
1082 if (XVT.isVector()) in shouldTransformSignedTruncationCheck()
1093 return VTIsOk(XVT) && VTIsOk(KeptBitsVT); in shouldTransformSignedTruncationCheck()
H A DX86ISelDAGToDAG.cpp3726 MVT XVT = X.getSimpleValueType(); in matchBitExtract() local
3762 if (XVT != MVT::i32) { in matchBitExtract()
3763 Control = CurDAG->getNode(ISD::ANY_EXTEND, DL, XVT, Control); in matchBitExtract()
3768 SDValue Extract = CurDAG->getNode(X86ISD::BEXTR, DL, XVT, X, Control); in matchBitExtract()
3771 if (XVT != NVT) { in matchBitExtract()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp3770 EVT XVT = X.getValueType(); in optimizeSetCCOfSignedTruncationCheck() local
3805 assert(XVT.isInteger()); in optimizeSetCCOfSignedTruncationCheck()
3806 NewCond = getSetCCInverse(NewCond, XVT); in optimizeSetCCOfSignedTruncationCheck()
3819 assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable"); in optimizeSetCCOfSignedTruncationCheck()
3824 XVT, KeptBits)) in optimizeSetCCOfSignedTruncationCheck()
3827 const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits; in optimizeSetCCOfSignedTruncationCheck()
3828 assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable"); in optimizeSetCCOfSignedTruncationCheck()
3832 SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT); in optimizeSetCCOfSignedTruncationCheck()
3833 SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt); in optimizeSetCCOfSignedTruncationCheck()
3834 SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt); in optimizeSetCCOfSignedTruncationCheck()
H A DDAGCombiner.cpp5262 EVT XVT = X.getValueType(); in hoistLogicOpWithSameOpcodeHands() local
5271 if (XVT != Y.getValueType()) in hoistLogicOpWithSameOpcodeHands()
5276 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
5281 !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
5284 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
5295 if (XVT != Y.getValueType()) in hoistLogicOpWithSameOpcodeHands()
5302 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT)) in hoistLogicOpWithSameOpcodeHands()
5304 if (!TLI.isTypeLegal(XVT)) in hoistLogicOpWithSameOpcodeHands()
5341 if (XVT.isInteger() && XVT == Y.getValueType() && in hoistLogicOpWithSameOpcodeHands()
5343 !XVT.isVector() && !TLI.isTypeLegal(XVT))) { in hoistLogicOpWithSameOpcodeHands()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h756 virtual bool shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3075 EVT XVT = X.getValueType(); in performShlCombine() local
3076 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()